[PATCH] D24857: Assign cost of scaling used in addressing mode for ARM cores

[James Molloy via llvm-commits]

jmolloy added a subscriber: jmolloy.

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Comment at: lib/Target/ARM/ARMISelLowering.cpp:11434
@@ +11433,3 @@
+  if (isLegalAddressingMode(DL, AM, Ty, AS))
+    return AM.Scale < 0 ? 2 : 0; // negative scaling costs extra cycles
+  return -1;
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Where did "2" come from here? Why not "1"? (a rationale would be useful)

This seems very broad-brush. I'd like to see it restricted down to a number of cores where this actually costs cycles. I have no idea if Apple's cores have this property, for example. And do our large cores, like Cortex-A72?


https://reviews.llvm.org/D24857