[PATCH] D24857: Assign cost of scaling used in addressing mode for ARM cores

[Javed Absar via llvm-commits]

javed.absar created this revision.
javed.absar added reviewers: rengolin, t.p.northover.
javed.absar added a subscriber: llvm-commits.
Herald added subscribers: samparker, rengolin, aemerson.

This patch assigns cost of the scaling used in addressing. On many ARM cores, a negated register offset takes longer than a non-negated register offset in a register-offset addressing mode. For instance:

  1.  LDR  R0, [R1, R2 LSL #2]  
  2.  LDR  R0, [R1, -R2 LSL #2]

Above, (1) takes less cycles than (2).

By assigning appropriate scaling factor cost, we enable the LLVM to make the right trade-offs in the optimization and code-selection phase.
 
The patch improves the performance as follows –
  Cortex-A53 :   spec.twolf:  2.4%, ShootoutC++_matrix: 28.4%,  Stanford/Puzzle:  12.4%, IndirectAddressing-dbl:  5.49%
  Cortex-A57 :  spec2006.hmmer: 1.5% , spec2006.lbm: 1.1%
 
The patch also improves performance on other third-party benchmarks


https://reviews.llvm.org/D24857

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  test/CodeGen/ARM/lsr-scale-addr-mode.ll

Index: test/CodeGen/ARM/lsr-scale-addr-mode.ll
===================================================================
--- test/CodeGen/ARM/lsr-scale-addr-mode.ll
+++ test/CodeGen/ARM/lsr-scale-addr-mode.ll
@@ -1,6 +1,9 @@
 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
 ; Should use scaled addressing mode.
 
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
+; Should not generate negated register offset
+
 define void @sintzero(i32* %a) nounwind {
 entry:
 	store i32 0, i32* %a
@@ -19,4 +22,5 @@
 }
 
 ; CHECK: lsl{{.*}}#2]
+; CHECK-NONEGOFF: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
 
Index: lib/Target/ARM/ARMISelLowering.h
===================================================================
--- lib/Target/ARM/ARMISelLowering.h
+++ lib/Target/ARM/ARMISelLowering.h
@@ -291,6 +291,14 @@
     /// by AM is legal for this target, for a load/store of the specified type.
     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
                                Type *Ty, unsigned AS) const override;
+
+    /// getScalingFactorCost - Return the cost of the scaling used in
+    /// addressing mode represented by AM.
+    /// If the AM is supported, the return value must be >= 0.
+    /// If the AM is not supported, the return value must be negative.
+    int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
+                             unsigned AS) const override;
+
     bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
 
     /// isLegalICmpImmediate - Return true if the specified immediate is legal
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -11427,6 +11427,14 @@
   return true;
 }
 
+int ARMTargetLowering::getScalingFactorCost(const DataLayout &DL,
+                                                const AddrMode &AM, Type *Ty,
+                                                unsigned AS) const {
+  if (isLegalAddressingMode(DL, AM, Ty, AS))
+    return AM.Scale < 0 ? 2 : 0; // negative scaling costs extra cycles
+  return -1;
+}
+
 
 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
   if (V < 0)


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