[PATCH] D22509: [X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 19 06:13:10 PDT 2016


RKSimon created this revision.
RKSimon added reviewers: qcolombet, ab, spatel, andreadb.
RKSimon added a subscriber: llvm-commits.
RKSimon set the repository for this revision to rL LLVM.

Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW.

But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register.

This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41).

I can commit these separately but included them together for review.

Fix for PR27265.

Repository:
  rL LLVM

https://reviews.llvm.org/D22509

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/2011-12-8-bitcastintprom.ll
  test/CodeGen/X86/avx512-trunc.ll
  test/CodeGen/X86/extract-store.ll
  test/CodeGen/X86/lower-vec-shift-2.ll
  test/CodeGen/X86/masked_memop.ll
  test/CodeGen/X86/trunc-ext-ld-st.ll
  test/CodeGen/X86/vector-shift-ashr-128.ll
  test/CodeGen/X86/vector-shift-ashr-256.ll
  test/CodeGen/X86/vector-shift-ashr-512.ll
  test/CodeGen/X86/vector-shift-lshr-128.ll
  test/CodeGen/X86/vector-shift-lshr-256.ll
  test/CodeGen/X86/vector-shift-lshr-512.ll
  test/CodeGen/X86/vector-shift-shl-128.ll
  test/CodeGen/X86/vector-shift-shl-256.ll
  test/CodeGen/X86/vector-shift-shl-512.ll
  test/CodeGen/X86/widen_conv-1.ll
  test/CodeGen/X86/widen_load-2.ll

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