[PATCH] D22509: [X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element

[Sanjay Patel via llvm-commits]

spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.

LGTM - one refactoring suggestion inline.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:12531-12545
@@ -12520,15 +12530,17 @@
   // TODO: handle v16i8.
   if (VT.getSizeInBits() == 16) {
-    if (IdxVal == 0)
+    // If Idx is 0, it's cheaper to do a move instead of a pextrw, unless we're
+    // going to zero extend the register.
+    if (IdxVal == 0 && !MayFoldIntoZeroExtend(Op))
       return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
                          DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
                                      DAG.getBitcast(MVT::v4i32, Vec), Idx));
 
     // Transform it so it match pextrw which produces a 32-bit result.
     MVT EltVT = MVT::i32;
     SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, Vec, Idx);
     SDValue Assert  = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
                                   DAG.getValueType(VT));
     return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
   }
 
----------------
Can you pull this chunk (if bitsize == 16 {}) out as a helper function so we don't have 2 copies of it?


Repository:
  rL LLVM

https://reviews.llvm.org/D22509