[PATCH] D19825: Power9 - Add exploitation of vector load and store that do not require swaps

[Kit Barton via llvm-commits]

kbarton requested changes to this revision.
kbarton added a comment.
This revision now requires changes to proceed.

As Eric suggested, remove the old patterns to ensure LXVX/STXVX instructions are generated, instead of using AddedComplexity.


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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:2161
@@ +2160,3 @@
+
+  let AddedComplexity = 500 in {
+    def : Pat<(v2f64 (load xoaddr:$src)), (LXVX xoaddr:$src)>;
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echristo wrote:
> Can we just exclude the other patterns? We don't ever want them to show up do we?
I agree, it would be better to just use the LXVX and STXVX instructions when they are available.
So, we would need to remove the previous patterns for ISA3_0, but keep them for older ISAs. 


Repository:
  rL LLVM

http://reviews.llvm.org/D19825