[PATCH] D19825: Power9 - Add exploitation of vector load and store that do not require swaps

[Nemanja Ivanovic via llvm-commits]

nemanjai added inline comments.

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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:2161
@@ +2160,3 @@
+
+  let AddedComplexity = 500 in {
+    def : Pat<(v2f64 (load xoaddr:$src)), (LXVX xoaddr:$src)>;
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kbarton wrote:
> echristo wrote:
> > Can we just exclude the other patterns? We don't ever want them to show up do we?
> I agree, it would be better to just use the LXVX and STXVX instructions when they are available.
> So, we would need to remove the previous patterns for ISA3_0, but keep them for older ISAs. 
@kbarton @echristo
Can you just elaborate a bit on what you mean by removing the other patterns?
If I remove all the patterns that generate `LXV[DW][24]X/STXV[WD][24]X`, we have will likely have issues on Power8 (assuming that these patterns were needed). So perhaps what I can do is predicate all the patterns for the old instructions with `IsPreISA3_0` (which would be `!Subtarget.isISA3_0()`). Maybe even `needSwapsForVSXMemoryOps()`.Then I wouldn't need the `AddedComplexity`.


Repository:
  rL LLVM

http://reviews.llvm.org/D19825