[PATCH] D22038: [X86] Transform zext+seteq+cmp into shr+lzcnt on btver2 architecture.

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Wed Jul 6 07:08:01 PDT 2016

RKSimon added a comment.

This seems to be limited to (a==0) and ((a== 0) || (b== 0)) patterns - is that the best way to do this? Can this be easily compounded to support different numbers of tests?

Comment at: lib/Target/X86/X86Subtarget.h:137
@@ -135,1 +136,3 @@
+  bool HasFastLZCNT;
   /// Processor has BMI1 instructions.
This isn't a processor/cpuid feature, please move this further down to be closer to the other fast/slow characteristic features.

Comment at: test/CodeGen/X86/lzcnt-zext-cmp.ll:1
@@ +1,2 @@
+; Test patterns which generates lzcnt instructions.
+; Eg: zext(setcc(cmp)) -> shr(lzcnt)
Please regenerate with utils/update_llc_test_checks.py


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