[PATCH] D16625: [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions

[Hrvoje Varga via llvm-commits]

hvarga added a subscriber: mamidzic.
hvarga updated this revision to Diff 61639.
hvarga added a comment.

Added MM64R6 case to LowerLargeShift and encodeInstruction for DSRL instruction.
Added BaseopCode and Arch to the classes that were missing it in order for instructions to appear in mapping tables.
Added StdMMR6Rel to LD, LLD, LWU, SD, DSRL, DSRL32, DSRLV
Added R6MMRel to LLD.
Changed FM classes so that they inherit from MipsR6Inst and MMR6Arch.
Changed DESC classes for the instructions so that they don't inherit MipsInst.
Joined NotInMicroMips blocks together where possible.
Changed LLD and LLD_R6 mem operand to mem_simm16.
Changed and added some tests.

This update has been contributed by @mamidzic.


http://reviews.llvm.org/D16625

Files:
  lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
  lib/Target/Mips/MicroMips64r6InstrFormats.td
  lib/Target/Mips/MicroMips64r6InstrInfo.td
  lib/Target/Mips/MicroMipsInstrFormats.td
  lib/Target/Mips/MicroMipsInstrInfo.td
  lib/Target/Mips/Mips32r6InstrInfo.td
  lib/Target/Mips/Mips64InstrInfo.td
  lib/Target/Mips/Mips64r6InstrInfo.td
  lib/Target/Mips/MipsInstrInfo.td
  test/CodeGen/Mips/lw16-base-reg.ll
  test/MC/Disassembler/Mips/micromips64r6/valid.txt
  test/MC/Mips/micromips-invalid.s
  test/MC/Mips/micromips64r6/invalid-wrong-error.s
  test/MC/Mips/micromips64r6/invalid.s
  test/MC/Mips/micromips64r6/valid.s
  test/MC/Mips/mips1/invalid-mips3-wrong-error.s
  test/MC/Mips/mips1/invalid-mips3.s
  test/MC/Mips/mips1/invalid-mips4-wrong-error.s
  test/MC/Mips/mips1/invalid-mips4.s
  test/MC/Mips/mips2/invalid-mips3-wrong-error.s
  test/MC/Mips/mips2/invalid-mips3.s
  test/MC/Mips/mips2/invalid-mips4-wrong-error.s
  test/MC/Mips/mips2/invalid-mips4.s
  test/MC/Mips/mips64r3/invalid.s
  test/MC/Mips/mips64r5/invalid.s
  test/MC/Mips/mips64r6/invalid.s

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