[llvm] r270982 - Apply clang-tidy's misc-static-assert where it makes sense.
Sean Silva via llvm-commits
llvm-commits at lists.llvm.org
Fri May 27 14:08:59 PDT 2016
Nice! This seems like a handy clang-tidy check!
On Fri, May 27, 2016 at 4:36 AM, Benjamin Kramer via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: d0k
> Date: Fri May 27 06:36:04 2016
> New Revision: 270982
>
> URL: http://llvm.org/viewvc/llvm-project?rev=270982&view=rev
> Log:
> Apply clang-tidy's misc-static-assert where it makes sense.
>
> Also fold conditions into assert(0) where it makes sense. No functional
> change intended.
>
> Modified:
> llvm/trunk/lib/CodeGen/DFAPacketizer.cpp
> llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp
> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
> llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
>
> Modified: llvm/trunk/lib/CodeGen/DFAPacketizer.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=270982&r1=270981&r2=270982&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/DFAPacketizer.cpp (original)
> +++ llvm/trunk/lib/CodeGen/DFAPacketizer.cpp Fri May 27 06:36:04 2016
> @@ -60,10 +60,12 @@ DFAPacketizer::DFAPacketizer(const Instr
> InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
> DFAStateEntryTable(SET) {
> // Make sure DFA types are large enough for the number of terms &
> resources.
> - assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAInput))
> - && "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput");
> - assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 *
> sizeof(DFAStateInput))
> - && "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for
> DFAStateInput");
> + static_assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <=
> + (8 * sizeof(DFAInput)),
> + "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for
> DFAInput");
> + static_assert(
> + (DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 *
> sizeof(DFAStateInput)),
> + "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");
> }
>
>
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=270982&r1=270981&r2=270982&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Fri May 27 06:36:04
> 2016
> @@ -1607,8 +1607,8 @@ unsigned AArch64FastISel::emitLogicalOp(
> unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
> unsigned LHSReg, bool
> LHSIsKill,
> uint64_t Imm) {
> - assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
> - "ISD nodes are not consecutive!");
> + static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
> + "ISD nodes are not consecutive!");
> static const unsigned OpcTable[3][2] = {
> { AArch64::ANDWri, AArch64::ANDXri },
> { AArch64::ORRWri, AArch64::ORRXri },
> @@ -1654,8 +1654,8 @@ unsigned AArch64FastISel::emitLogicalOp_
> unsigned LHSReg, bool
> LHSIsKill,
> unsigned RHSReg, bool
> RHSIsKill,
> uint64_t ShiftImm) {
> - assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
> - "ISD nodes are not consecutive!");
> + static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
> + "ISD nodes are not consecutive!");
> static const unsigned OpcTable[3][2] = {
> { AArch64::ANDWrs, AArch64::ANDXrs },
> { AArch64::ORRWrs, AArch64::ORRXrs },
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=270982&r1=270981&r2=270982&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Fri May 27 06:36:04
> 2016
> @@ -1447,8 +1447,8 @@ bool AArch64InstrInfo::isScaledAddr(cons
>
> /// Check all MachineMemOperands for a hint to suppress pairing.
> bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr *MI) const
> {
> - assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
> - "Too many target MO flags");
> + static_assert(MOSuppressPair < (1 <<
> MachineMemOperand::MOTargetNumBits),
> + "Too many target MO flags");
> for (auto *MM : MI->memoperands()) {
> if (MM->getFlags() &
> (MOSuppressPair << MachineMemOperand::MOTargetStartBit)) {
> @@ -1463,8 +1463,8 @@ void AArch64InstrInfo::suppressLdStPair(
> if (MI->memoperands_empty())
> return;
>
> - assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
> - "Too many target MO flags");
> + static_assert(MOSuppressPair < (1 <<
> MachineMemOperand::MOTargetNumBits),
> + "Too many target MO flags");
> (*MI->memoperands_begin())
> ->setFlags(MOSuppressPair << MachineMemOperand::MOTargetStartBit);
> }
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp?rev=270982&r1=270981&r2=270982&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp Fri May 27
> 06:36:04 2016
> @@ -522,12 +522,9 @@ void SIScheduleBlock::addPred(SISchedule
> }
> Preds.push_back(Pred);
>
> -#ifndef NDEBUG
> - for (SIScheduleBlock* S : Succs) {
> - if (PredID == S->getID())
> - assert(!"Loop in the Block Graph!\n");
> - }
> -#endif
> + assert(none_of(Succs,
> + [=](SIScheduleBlock *S) { return PredID == S->getID();
> }) &&
> + "Loop in the Block Graph!");
> }
>
> void SIScheduleBlock::addSucc(SIScheduleBlock *Succ) {
> @@ -541,12 +538,9 @@ void SIScheduleBlock::addSucc(SISchedule
> if (Succ->isHighLatencyBlock())
> ++NumHighLatencySuccessors;
> Succs.push_back(Succ);
> -#ifndef NDEBUG
> - for (SIScheduleBlock* P : Preds) {
> - if (SuccID == P->getID())
> - assert(!"Loop in the Block Graph!\n");
> - }
> -#endif
> + assert(none_of(Preds,
> + [=](SIScheduleBlock *P) { return SuccID == P->getID();
> }) &&
> + "Loop in the Block Graph!");
> }
>
> #ifndef NDEBUG
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=270982&r1=270981&r2=270982&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri May 27 06:36:04 2016
> @@ -1936,8 +1936,9 @@ void ARMDAGToDAGISel::SelectVLD(SDNode *
>
> // Extract out the subregisters.
> SDValue SuperReg = SDValue(VLd, 0);
> - assert(ARM::dsub_7 == ARM::dsub_0+7 &&
> - ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
> + static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
> + ARM::qsub_3 == ARM::qsub_0 + 3,
> + "Unexpected subreg numbering");
> unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
> for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
> ReplaceUses(SDValue(N, Vec),
> @@ -2205,8 +2206,9 @@ void ARMDAGToDAGISel::SelectVLDSTLane(SD
>
> // Extract the subregisters.
> SuperReg = SDValue(VLdLn, 0);
> - assert(ARM::dsub_7 == ARM::dsub_0+7 &&
> - ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
> + static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
> + ARM::qsub_3 == ARM::qsub_0 + 3,
> + "Unexpected subreg numbering");
> unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
> for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
> ReplaceUses(SDValue(N, Vec),
> @@ -2288,7 +2290,7 @@ void ARMDAGToDAGISel::SelectVLDDup(SDNod
> SuperReg = SDValue(VLdDup, 0);
>
> // Extract the subregisters.
> - assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
> + static_assert(ARM::dsub_7 == ARM::dsub_0 + 7, "Unexpected subreg
> numbering");
> unsigned SubIdx = ARM::dsub_0;
> for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
> ReplaceUses(SDValue(N, Vec),
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=270982&r1=270981&r2=270982&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp Fri May 27
> 06:36:04 2016
> @@ -222,8 +222,8 @@ namespace {
> /// Returns the callee saved register with the largest id in the vector.
> unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI,
> const TargetRegisterInfo &TRI) {
> - assert(Hexagon::R1 > 0 &&
> - "Assume physical registers are encoded as positive integers");
> + static_assert(Hexagon::R1 > 0,
> + "Assume physical registers are encoded as positive
> integers");
> if (CSI.empty())
> return 0;
>
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp?rev=270982&r1=270981&r2=270982&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp Fri May 27
> 06:36:04 2016
> @@ -155,7 +155,7 @@ unsigned HexagonGenPredicate::getPredFor
> // The opcode corresponding to 0 is TargetOpcode::PHI. We can use 0 here
> // to denote "none", but we need to make sure that none of the valid
> opcodes
> // that we return will ever be 0.
> - assert(PHI == 0 && "Use different value for <none>");
> + static_assert(PHI == 0, "Use different value for <none>");
> return 0;
> }
>
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=270982&r1=270981&r2=270982&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Fri May 27 06:36:04
> 2016
> @@ -185,7 +185,8 @@ static bool CC_Sparc64_Half(unsigned &Va
> // callee's register window. This function translates registers to the
> // corresponding caller window %o register.
> static unsigned toCallerWindow(unsigned Reg) {
> - assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected
> enum");
> + static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
> + "Unexpected enum");
> if (Reg >= SP::I0 && Reg <= SP::I7)
> return Reg - SP::I0 + SP::O0;
> return Reg;
>
>
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