<div dir="ltr">Nice! This seems like a handy clang-tidy check!</div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, May 27, 2016 at 4:36 AM, Benjamin Kramer via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: d0k<br>
Date: Fri May 27 06:36:04 2016<br>
New Revision: 270982<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=270982&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=270982&view=rev</a><br>
Log:<br>
Apply clang-tidy's misc-static-assert where it makes sense.<br>
<br>
Also fold conditions into assert(0) where it makes sense. No functional<br>
change intended.<br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/DFAPacketizer.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp<br>
llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/DFAPacketizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=270982&r1=270981&r2=270982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=270982&r1=270981&r2=270982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/DFAPacketizer.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/DFAPacketizer.cpp Fri May 27 06:36:04 2016<br>
@@ -60,10 +60,12 @@ DFAPacketizer::DFAPacketizer(const Instr<br>
InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),<br>
DFAStateEntryTable(SET) {<br>
// Make sure DFA types are large enough for the number of terms & resources.<br>
- assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAInput))<br>
- && "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput");<br>
- assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAStateInput))<br>
- && "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");<br>
+ static_assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <=<br>
+ (8 * sizeof(DFAInput)),<br>
+ "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput");<br>
+ static_assert(<br>
+ (DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAStateInput)),<br>
+ "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");<br>
}<br>
<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=270982&r1=270981&r2=270982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=270982&r1=270981&r2=270982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Fri May 27 06:36:04 2016<br>
@@ -1607,8 +1607,8 @@ unsigned AArch64FastISel::emitLogicalOp(<br>
unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,<br>
unsigned LHSReg, bool LHSIsKill,<br>
uint64_t Imm) {<br>
- assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&<br>
- "ISD nodes are not consecutive!");<br>
+ static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),<br>
+ "ISD nodes are not consecutive!");<br>
static const unsigned OpcTable[3][2] = {<br>
{ AArch64::ANDWri, AArch64::ANDXri },<br>
{ AArch64::ORRWri, AArch64::ORRXri },<br>
@@ -1654,8 +1654,8 @@ unsigned AArch64FastISel::emitLogicalOp_<br>
unsigned LHSReg, bool LHSIsKill,<br>
unsigned RHSReg, bool RHSIsKill,<br>
uint64_t ShiftImm) {<br>
- assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&<br>
- "ISD nodes are not consecutive!");<br>
+ static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),<br>
+ "ISD nodes are not consecutive!");<br>
static const unsigned OpcTable[3][2] = {<br>
{ AArch64::ANDWrs, AArch64::ANDXrs },<br>
{ AArch64::ORRWrs, AArch64::ORRXrs },<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=270982&r1=270981&r2=270982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=270982&r1=270981&r2=270982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Fri May 27 06:36:04 2016<br>
@@ -1447,8 +1447,8 @@ bool AArch64InstrInfo::isScaledAddr(cons<br>
<br>
/// Check all MachineMemOperands for a hint to suppress pairing.<br>
bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr *MI) const {<br>
- assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&<br>
- "Too many target MO flags");<br>
+ static_assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits),<br>
+ "Too many target MO flags");<br>
for (auto *MM : MI->memoperands()) {<br>
if (MM->getFlags() &<br>
(MOSuppressPair << MachineMemOperand::MOTargetStartBit)) {<br>
@@ -1463,8 +1463,8 @@ void AArch64InstrInfo::suppressLdStPair(<br>
if (MI->memoperands_empty())<br>
return;<br>
<br>
- assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&<br>
- "Too many target MO flags");<br>
+ static_assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits),<br>
+ "Too many target MO flags");<br>
(*MI->memoperands_begin())<br>
->setFlags(MOSuppressPair << MachineMemOperand::MOTargetStartBit);<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp?rev=270982&r1=270981&r2=270982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp?rev=270982&r1=270981&r2=270982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp Fri May 27 06:36:04 2016<br>
@@ -522,12 +522,9 @@ void SIScheduleBlock::addPred(SISchedule<br>
}<br>
Preds.push_back(Pred);<br>
<br>
-#ifndef NDEBUG<br>
- for (SIScheduleBlock* S : Succs) {<br>
- if (PredID == S->getID())<br>
- assert(!"Loop in the Block Graph!\n");<br>
- }<br>
-#endif<br>
+ assert(none_of(Succs,<br>
+ [=](SIScheduleBlock *S) { return PredID == S->getID(); }) &&<br>
+ "Loop in the Block Graph!");<br>
}<br>
<br>
void SIScheduleBlock::addSucc(SIScheduleBlock *Succ) {<br>
@@ -541,12 +538,9 @@ void SIScheduleBlock::addSucc(SISchedule<br>
if (Succ->isHighLatencyBlock())<br>
++NumHighLatencySuccessors;<br>
Succs.push_back(Succ);<br>
-#ifndef NDEBUG<br>
- for (SIScheduleBlock* P : Preds) {<br>
- if (SuccID == P->getID())<br>
- assert(!"Loop in the Block Graph!\n");<br>
- }<br>
-#endif<br>
+ assert(none_of(Preds,<br>
+ [=](SIScheduleBlock *P) { return SuccID == P->getID(); }) &&<br>
+ "Loop in the Block Graph!");<br>
}<br>
<br>
#ifndef NDEBUG<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=270982&r1=270981&r2=270982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=270982&r1=270981&r2=270982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri May 27 06:36:04 2016<br>
@@ -1936,8 +1936,9 @@ void ARMDAGToDAGISel::SelectVLD(SDNode *<br>
<br>
// Extract out the subregisters.<br>
SDValue SuperReg = SDValue(VLd, 0);<br>
- assert(ARM::dsub_7 == ARM::dsub_0+7 &&<br>
- ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");<br>
+ static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&<br>
+ ARM::qsub_3 == ARM::qsub_0 + 3,<br>
+ "Unexpected subreg numbering");<br>
unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);<br>
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)<br>
ReplaceUses(SDValue(N, Vec),<br>
@@ -2205,8 +2206,9 @@ void ARMDAGToDAGISel::SelectVLDSTLane(SD<br>
<br>
// Extract the subregisters.<br>
SuperReg = SDValue(VLdLn, 0);<br>
- assert(ARM::dsub_7 == ARM::dsub_0+7 &&<br>
- ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");<br>
+ static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&<br>
+ ARM::qsub_3 == ARM::qsub_0 + 3,<br>
+ "Unexpected subreg numbering");<br>
unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;<br>
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)<br>
ReplaceUses(SDValue(N, Vec),<br>
@@ -2288,7 +2290,7 @@ void ARMDAGToDAGISel::SelectVLDDup(SDNod<br>
SuperReg = SDValue(VLdDup, 0);<br>
<br>
// Extract the subregisters.<br>
- assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");<br>
+ static_assert(ARM::dsub_7 == ARM::dsub_0 + 7, "Unexpected subreg numbering");<br>
unsigned SubIdx = ARM::dsub_0;<br>
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)<br>
ReplaceUses(SDValue(N, Vec),<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=270982&r1=270981&r2=270982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=270982&r1=270981&r2=270982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp Fri May 27 06:36:04 2016<br>
@@ -222,8 +222,8 @@ namespace {<br>
/// Returns the callee saved register with the largest id in the vector.<br>
unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI,<br>
const TargetRegisterInfo &TRI) {<br>
- assert(Hexagon::R1 > 0 &&<br>
- "Assume physical registers are encoded as positive integers");<br>
+ static_assert(Hexagon::R1 > 0,<br>
+ "Assume physical registers are encoded as positive integers");<br>
if (CSI.empty())<br>
return 0;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp?rev=270982&r1=270981&r2=270982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp?rev=270982&r1=270981&r2=270982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp Fri May 27 06:36:04 2016<br>
@@ -155,7 +155,7 @@ unsigned HexagonGenPredicate::getPredFor<br>
// The opcode corresponding to 0 is TargetOpcode::PHI. We can use 0 here<br>
// to denote "none", but we need to make sure that none of the valid opcodes<br>
// that we return will ever be 0.<br>
- assert(PHI == 0 && "Use different value for <none>");<br>
+ static_assert(PHI == 0, "Use different value for <none>");<br>
return 0;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=270982&r1=270981&r2=270982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=270982&r1=270981&r2=270982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Fri May 27 06:36:04 2016<br>
@@ -185,7 +185,8 @@ static bool CC_Sparc64_Half(unsigned &Va<br>
// callee's register window. This function translates registers to the<br>
// corresponding caller window %o register.<br>
static unsigned toCallerWindow(unsigned Reg) {<br>
- assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");<br>
+ static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,<br>
+ "Unexpected enum");<br>
if (Reg >= SP::I0 && Reg <= SP::I7)<br>
return Reg - SP::I0 + SP::O0;<br>
return Reg;<br>
<br>
<br>
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</blockquote></div><br></div>