[PATCH] D20649: [X86] Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid falsely marking whole 32 bit register as live.

[Kevin B. Smith via llvm-commits]

kbsmith1 created this revision.
kbsmith1 added reviewers: DavidKreitzer, spatel.
kbsmith1 added a subscriber: llvm-commits.

This just adds a new pattern for using AH for an 8 bit right shift from a 16 bit value rather than
from a 32 bit value.  This prevents use of GR32_ABCD pattern, and a dummy upward conversion.
This makes the register liveness a little more accurate for post register allocation analysis.

http://reviews.llvm.org/D20649

Files:
  lib/Target/X86/X86InstrCompiler.td
  test/CodeGen/X86/i16lshr8pat.ll

Index: lib/Target/X86/X86InstrCompiler.td
===================================================================
--- lib/Target/X86/X86InstrCompiler.td
+++ lib/Target/X86/X86InstrCompiler.td
@@ -1550,6 +1550,10 @@
           (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
                           sub_8bit_hi)>,
       Requires<[Not64BitMode]>;
+def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))),
+          (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
+                          sub_8bit_hi)>,
+      Requires<[Not64BitMode]>;
 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
           (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
                           sub_8bit_hi)>,
Index: test/CodeGen/X86/i16lshr8pat.ll
===================================================================
--- test/CodeGen/X86/i16lshr8pat.ll
+++ test/CodeGen/X86/i16lshr8pat.ll
@@ -0,0 +1,31 @@
+; RUN: llc -march=x86 -print-after=expand-isel-pseudos <%s 2>&1 | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i386-unknown-linux-gnu"
+
+; This test checks to make sure the lshr in %then1 block gets expanded using
+; GR16_ABCD pattern rather than GR32_ABCD pattern.  By using the 16 bit pattern
+; this doesn't make the register liveness information look like the whole 32
+; bit register is a live value, and allows generally better live register
+; analysis.
+; CHECK-LABEL: BB#1:
+; CHECK: GR16_ABCD
+; CHECK-NOT: GR32_ABCD
+; CHECK-LABEL: BB#2:
+
+define i16 @foo4(i32 %prec, i8 *%dst, i16 *%src) {
+entry:
+  %cnd = icmp ne i32 %prec, 0
+  %t0 = load i16, i16 *%src, align 2
+  br i1 %cnd, label %then1, label %endif1
+
+then1:
+  %shr = lshr i16 %t0, 8
+  %conv = trunc i16 %shr to i8
+  store i8 %conv, i8 *%dst, align 1
+  br label %endif1
+
+endif1:
+  %t2 = phi i16 [0, %then1], [%t0, %entry]
+  ret i16 %t2
+}


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D20649.58530.patch
Type: text/x-patch
Size: 1919 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160525/7beb1f3e/attachment.bin>