[llvm] r267901 - [Hexagon] Define certain aliases for vector instructions

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu Apr 28 11:43:16 2016
New Revision: 267901

URL: http://llvm.org/viewvc/llvm-project?rev=267901&view=rev
Log:
[Hexagon] Define certain aliases for vector instructions

Specifically:
  Vd = #0   -> Vd = vxor(Vd, Vd)
  Vdd = #0  -> Vdd.w = vsub(Vdd.w, Vdd.w)
  Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L)

Added:
    llvm/trunk/lib/Target/Hexagon/HexagonAlias.td
    llvm/trunk/test/MC/Hexagon/v60-misc.s
Modified:
    llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
    llvm/trunk/lib/Target/Hexagon/Hexagon.td

Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=267901&r1=267900&r2=267901&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Thu Apr 28 11:43:16 2016
@@ -1658,6 +1658,19 @@ int HexagonAsmParser::processInstruction
     break;
   }
 
+  // Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)"
+  case Hexagon::HEXAGON_V6_vassignpair: {
+    MCOperand &MO = Inst.getOperand(1);
+    unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
+    std::string R1 = v + llvm::utostr(RegPairNum + 1);
+    MO.setReg(MatchRegisterName(R1));
+    // Add a new operand for the second register in the pair.
+    std::string R2 = v + llvm::utostr(RegPairNum);
+    Inst.addOperand(MCOperand::createReg(MatchRegisterName(R2)));
+    Inst.setOpcode(Hexagon::V6_vcombine);
+    break;
+  }
+
   // Translate a "$Rx =  CONST32(#imm)" to "$Rx = memw(gp+#LABEL) "
   case Hexagon::CONST32:
   case Hexagon::CONST32_Float_Real:

Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=267901&r1=267900&r2=267901&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Thu Apr 28 11:43:16 2016
@@ -227,6 +227,7 @@ include "HexagonCallingConv.td"
 include "HexagonInstrInfo.td"
 include "HexagonIntrinsics.td"
 include "HexagonIntrinsicsDerived.td"
+include "HexagonAlias.td"
 
 def HexagonInstrInfo : InstrInfo;
 

Added: llvm/trunk/lib/Target/Hexagon/HexagonAlias.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAlias.td?rev=267901&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAlias.td (added)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAlias.td Thu Apr 28 11:43:16 2016
@@ -0,0 +1,29 @@
+//==- HexagonAlias.td - Hexagon Instruction Aliases ---------*- tablegen -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//                     Hexagon Instruction Mappings
+//===----------------------------------------------------------------------===//
+
+// V6_vassignp: Vector assign mapping.
+let hasNewValue = 1, opNewValue = 0, isAsmParserOnly = 1 in
+def HEXAGON_V6_vassignpair: CVI_VA_DV_Resource <
+  (outs VecDblRegs:$Vdd),
+  (ins VecDblRegs:$Vss),
+  "$Vdd = $Vss">;
+
+// maps Vd = #0 to Vd = vxor(Vd, Vd)
+def : InstAlias<"$Vd = #0",
+      (V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>,
+      Requires<[HasV60T]>;
+
+// maps Vdd  = #0 to Vdd = vsub(Vdd, Vdd)
+def : InstAlias<"$Vdd = #0",
+      (V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>,
+      Requires<[HasV60T]>;

Added: llvm/trunk/test/MC/Hexagon/v60-misc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/v60-misc.s?rev=267901&view=auto
==============================================================================
--- llvm/trunk/test/MC/Hexagon/v60-misc.s (added)
+++ llvm/trunk/test/MC/Hexagon/v60-misc.s Thu Apr 28 11:43:16 2016
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -d - | FileCheck %s
+
+# CHECK: 1c2eceee { v14 = vxor(v14,{{ *}}v14) }
+v14 = #0
+
+# CHECK: 1c80c0a0 { v1:0.w = vsub(v1:0.w,v1:0.w) }
+v1:0 = #0
+
+# CHECK: 1f42c3e0 { v1:0 = vcombine(v3,v2) }
+v1:0 = v3:2