[PATCH] D18453: AMDGPU/SI: Improve MachineSchedModel definition

[Matt Arsenault via llvm-commits]

arsenm added inline comments.

================
Comment at: lib/Target/AMDGPU/SISchedule.td:43
@@ +42,3 @@
+class SISchedMachineModel : SchedMachineModel {
+	let CompleteModel = 0;
+	let IssueWidth = 1;
----------------
Is there much more to do to complete the model?

================
Comment at: lib/Target/AMDGPU/SISchedule.td:50
@@ -51,2 +49,3 @@
 
 // XXX: Are the resource counts correct?
+def HWBranch : ProcResource<1> {
----------------
Is this comment still needed?

================
Comment at: test/CodeGen/AMDGPU/udivrem.ll:110
@@ -109,5 +109,3 @@
 
-; SI-DAG: v_rcp_iflag_f32_e32 [[FIRST_RCP:v[0-9]+]]
-; SI-DAG: v_mul_hi_u32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]]
-; SI-DAG: v_mul_lo_i32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]]
-; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], vcc, 0, [[FIRST_RCP_LO]]
+; For SI, we used to have tests checks for the input and output registers
+; of the instructions, but these are way too fragile.  The division for
----------------
Grammar: "tests checks"


http://reviews.llvm.org/D18453