[PATCH] D18453: AMDGPU/SI: Improve MachineSchedModel definition

[Tom Stellard via llvm-commits]

tstellarAMD created this revision.
tstellarAMD added reviewers: nhaehnle, arsenm.
tstellarAMD added a subscriber: llvm-commits.
tstellarAMD added dependencies: D18451: AMDGPU/SI: Limit load clustering to 16 bytes instead of 4 instructions, D18452: AMDGPU/SI: Enable lanemask tracking in misched.
Herald added a subscriber: arsenm.

This patch contains a few improvements to the model, including:

- Using a single resource with a defined buffers size for each memory unit.
- Setting the IssueWidth correctly.
- Fixing latency values for memory instructions.

shader-db stats:

16429 shaders in 3231 tests
Totals:
SGPRS: 318232 -> 312328 (-1.86 %)
VGPRS: 208996 -> 209346 (0.17 %)
Code Size: 7147044 -> 7166440 (0.27 %) bytes
LDS: 83 -> 83 (0.00 %) blocks
Scratch: 1862656 -> 1459200 (-21.66 %) bytes per wave
Max Waves: 49182 -> 49243 (0.12 %)
Wait states: 0 -> 0 (0.00 %)

Depends on D18451
Depends on D18452

http://reviews.llvm.org/D18453

Files:
  lib/Target/AMDGPU/SISchedule.td
  test/CodeGen/AMDGPU/ds_read2_offset_order.ll
  test/CodeGen/AMDGPU/fceil64.ll
  test/CodeGen/AMDGPU/ftrunc.f64.ll
  test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.f64.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
  test/CodeGen/AMDGPU/llvm.memcpy.ll
  test/CodeGen/AMDGPU/local-memory-two-objects.ll
  test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
  test/CodeGen/AMDGPU/udivrem.ll

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