[PATCH] D18307: [X86][SSE] Add MULHS/MULHU custom lowering for i8 vectors

[Quentin Colombet via llvm-commits]

qcolombet added inline comments.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:19053
@@ +19052,3 @@
+  if (VT.is256BitVector() && !Subtarget.hasInt256())
+    return Lower256IntArith(Op, DAG);
+
----------------
Right now, Subtarget.hasInt256() should be true for 256 bit vector, since we add the custom lowering for those only when this predicate is true.
I.e., this is dead code at the moment, right?

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:19078
@@ +19077,3 @@
+
+    return DAG.getNode(ISD::TRUNCATE, dl, VT,
+                       DAG.getNode(ISD::MUL, dl, MVT::v16i16,
----------------
This returns the low value, right?
I believe we miss a shift before the truncate.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:19094
@@ +19093,3 @@
+  } else {
+    const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
+                            -1, 4, -1, 5, -1, 6, -1, 7};
----------------
A few comments on how we achieve the extraction wouldn’t hurt :).

E.g., Fill the 8 high bits of a v8i16 vector with the low input vector.
Shift that vector right by 8, to put the 8 relevant bits at the right place and fill the 8 high bits with 0 or sign extension.


Repository:
  rL LLVM

http://reviews.llvm.org/D18307