[PATCH] D18307: [X86][SSE] Add MULHS/MULHU custom lowering for i8 vectors

[Simon Pilgrim via llvm-commits]

RKSimon updated this revision to Diff 51350.
RKSimon added a comment.

Revised based on Quentin's feedback.

Enabled v32i8 and v16i16 MULHS/MULHU custom lowering on AVX1 targets to prevent scalarization - I can commit the v16i16 support separately if necessary.

Improved the AVX 32i8 lowerings to make use ymm PACKUS (saves 2cy on my Carrizo tests) and added a missing shift to the v16i8 version (I had stupidly only locally tested 32i8 on AVX2 hardware).

Tried to improve comments on what is going on.


Repository:
  rL LLVM

http://reviews.llvm.org/D18307

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/vector-idiv-sdiv-128.ll
  test/CodeGen/X86/vector-idiv-sdiv-256.ll
  test/CodeGen/X86/vector-idiv-udiv-128.ll
  test/CodeGen/X86/vector-idiv-udiv-256.ll

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