[PATCH] D18097: [Power9] basic support for Power 9 direct move instructions
amehsan via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 17 04:11:52 PDT 2016
amehsan added inline comments.
Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1247
@@ +1246,3 @@
+ def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins gprc:$rA, gprc:$rB),
+ "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
> Why 32-bit register inputs? The instruction takes two doubleword inputs in 64-bit registers and puts them in the VSR. The inputs should probably be:
> (ins g8rc:$rA, g8rc:$rB).
That is an oversight. It does not impact encoding and decoding of the instruction, so testing was not able to catch it. That raises a quesiton: On Power8 and Power9 32 bit GPRs are the lower half of 64 bit GPRs and in 64 bit mode, the upper 32 bit cannot be accessed independently. So why do we need to distinguish between the two sets? I talked a little bit with other people and checked the source code and so far I do not have an answer for this question. One potential answer is that we need the distinction for processors that support some optional features of ISA, such as SPE. I will fix this anyway to be on the safe side.
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