[PATCH] D18097: [Power9] basic support for Power 9 direct move instructions

Nemanja Ivanovic via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 14 03:29:52 PDT 2016

nemanjai added inline comments.

Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1247
@@ +1246,3 @@
+  def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins gprc:$rA, gprc:$rB),
+                       "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
Why 32-bit register inputs? The instruction takes two doubleword inputs in 64-bit registers and puts them in the VSR. The inputs should probably be:
(ins g8rc:$rA, g8rc:$rB).

Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1251
@@ +1250,3 @@
+  def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs gprc:$rA), (ins vsrc:$XT),
+                              "mfvsrld $rA, $XT", IIC_VecGeneral,
Same thing here. The output should be a 64-bit register.


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