[PATCH] D17334: [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions

[Daniel Sanders via llvm-commits]

dsanders accepted this revision.
dsanders added a comment.
This revision is now accepted and ready to land.

LGTM with the missing MFHC1 for the FGR64 case and the indentation nits.


================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:580-581
@@ +579,4 @@
+class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd>;
+class MFHC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd,
+                                            II_MFHC1>, HARDFLOAT;
+class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>;
----------------
The FPU register width is independent of the CPU register width. You also need the 64-bit FPU case.

================
Comment at: lib/Target/Mips/MicroMips64r6InstrInfo.td:97-98
@@ +96,4 @@
+class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd>;
+class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
+                                              II_DMFC1, bitconvert>;
+class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd>;
----------------
I mentioned above that the FPU register width is independent of the CPU register width but we do guarantee that it's no smaller than the CPU register width so this is ok.

================
Comment at: test/MC/Mips/micromips32r6/invalid.s:110-113
@@ -109,1 +109,5 @@
   swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  mfc0  $4, $3, -1         # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
+  mfc0  $4, $3, 8          # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
+  mfhc0 $4, $3, -1         # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
+  mfhc0 $4, $3, 8          # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
----------------
Indentation on the '# CHECK'.
Similarly on some of the other tests.

================
Comment at: test/MC/Mips/micromips32r6/valid.s:253-260
@@ -252,1 +252,9 @@
   deret                    # CHECK: deret                  # encoding: [0x00,0x00,0xe3,0x7c]
+  mfc0 $3, $7              # CHECK: mfc0 $3, $7, 0      # encoding: [0x00,0x67,0x00,0xfc]
+  mfc0 $3, $7, 3           # CHECK: mfc0 $3, $7, 3      # encoding: [0x00,0x67,0x18,0xfc]
+  mfc1 $5, $f10            # CHECK: mfc1 $5, $f10       # encoding: [0x54,0xaa,0x20,0x3b]
+  mfc2 $15, $5             # CHECK: mfc2 $15, $5        # encoding: [0x01,0xe5,0x4d,0x3c]
+  mfhc0 $20, $21           # CHECK: mfhc0 $20, $21, 0   # encoding: [0x02,0x95,0x00,0xf4]
+  mfhc0 $1, $2, 1          # CHECK: mfhc0 $1, $2, 1     # encoding: [0x00,0x22,0x08,0xf4]
+  mfhc1 $zero, $f6         # CHECK: mfhc1 $zero, $f6    # encoding: [0x54,0x06,0x30,0x3b]
+  mfhc2 $23, $16           # CHECK: mfhc2 $23, $16      # encoding: [0x02,0xf0,0x8d,0x3c]
----------------
Indentation on the '# encoding'.
Similarly on some of the other tests.


http://reviews.llvm.org/D17334