[llvm] r261185 - [AMDGPU] Disassembler: Added basic disassembler for AMDGPU target
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 17 20:51:00 PST 2016
The comments here say that Targets.td was modified to support
DecoderMethod=“NONE”,
but that doesn't seem to be in the content.
On Wed, Feb 17, 2016 at 7:42 PM, Tom Stellard via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: tstellar
> Date: Wed Feb 17 21:42:32 2016
> New Revision: 261185
>
> URL: http://llvm.org/viewvc/llvm-project?rev=261185&view=rev
> Log:
> [AMDGPU] Disassembler: Added basic disassembler for AMDGPU target
>
> Changes:
>
> - Added disassembler project
> - Fixed all decoding conflicts in .td files
> - Added DecoderMethod=“NONE” option to Target.td that allows to
> disable decoder generation for an instruction.
> - Created decoding functions for VS_32 and VReg_32 register classes.
> - Added stubs for decoding all register classes.
> - Added several tests for disassembler
>
> Disassembler only supports:
>
> - VI subtarget
> - VOP1 instruction encoding
> - 32-bit register operands and inline constants
>
> [Valery]
>
> One of the point that requires to pay attention to is how decoder
> conflicts were resolved:
>
> - Groups of target instructions were separated by using different
> DecoderNamespace (SICI, VI, CI) using similar to AssemblerPredicate
> approach.
>
> - There were conflicts in IMAGE_<> instructions caused by two
> different reasons:
>
> 1. dmask wasn’t specified for the output (fixed)
> 2. There are image instructions that differ only by the number of
> the address components but have the same encoding by the HW spec. The
> actual number of address components is determined by the HW at runtime
> using image resource descriptor starting from the VGPR encoded in an
> IMAGE instruction. This means that we should choose only one instruction
> from conflicting group to be the rule for decoder. I didn’t find the way
> to disable decoder generation for an arbitrary instruction and therefore
> made a onelinear fix to tablegen generator that would suppress decoder
> generation when DecoderMethod is set to “NONE”. This is a change that
> should be reviewed and submitted first. Otherwise I would need to
> specify different DecoderNamespace for every instruction in the
> conflicting group. I haven’t checked yet if DecoderMethod=“NONE” is not
> used in other targets.
> 3. IMAGE_GATHER decoder generation is for now disabled and to be
> done later.
>
> [/Valery]
>
> Patch By: Sam Kolton
>
> Differential Revision: http://reviews.llvm.org/D16723
>
> Added:
> llvm/trunk/lib/Target/AMDGPU/Disassembler/
> llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
> llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
> llvm/trunk/lib/Target/AMDGPU/Disassembler/CMakeLists.txt
> llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt
> - copied, changed from r261176,
> llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt
> llvm/trunk/test/MC/Disassembler/AMDGPU/
> llvm/trunk/test/MC/Disassembler/AMDGPU/lit.local.cfg
> llvm/trunk/test/MC/Disassembler/AMDGPU/mov.txt
> llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt
> Modified:
> llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td
> llvm/trunk/lib/Target/AMDGPU/CIInstructions.td
> llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt
> llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt
> llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
> llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
> llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
> llvm/trunk/lib/Target/AMDGPU/VIInstructions.td
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=261185&r1=261184&r2=261185&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td Wed Feb 17 21:42:32
> 2016
> @@ -23,6 +23,14 @@ class AMDGPUInst <dag outs, dag ins, str
> let Pattern = pattern;
> let Itinerary = NullALU;
>
> + // SoftFail is a field the disassembler can use to provide a way for
> + // instructions to not match without killing the whole decode process.
> It is
> + // mainly used for ARM, but Tablegen expects this field to exist or it
> fails
> + // to build the decode table.
> + field bits<64> SoftFail = 0;
> +
> + let DecoderNamespace = Namespace;
> +
> let TSFlags{63} = isRegisterLoad;
> let TSFlags{62} = isRegisterStore;
> }
>
> Modified: llvm/trunk/lib/Target/AMDGPU/CIInstructions.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/CIInstructions.td?rev=261185&r1=261184&r2=261185&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/CIInstructions.td (original)
> +++ llvm/trunk/lib/Target/AMDGPU/CIInstructions.td Wed Feb 17 21:42:32 2016
> @@ -100,9 +100,11 @@ defm S_DCACHE_INV_VOL : SMRD_Inval <smrd
> // MUBUF Instructions
>
> //===----------------------------------------------------------------------===//
>
> +let DisableSIDecoder = 1 in {
> defm BUFFER_WBINVL1_VOL : MUBUF_Invalidate <mubuf<0x70, 0x3f>,
> "buffer_wbinvl1_vol", int_amdgcn_buffer_wbinvl1_vol
> >;
> +}
>
>
> //===----------------------------------------------------------------------===//
> // Flat Instructions
> @@ -233,7 +235,7 @@ defm FLAT_ATOMIC_DEC_X2 : FLAT_ATOMIC <
>
> // CI Only flat instructions
>
> -let SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst in {
> +let SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst,
> DisableVIDecoder = 1 in {
>
> defm FLAT_ATOMIC_FCMPSWAP : FLAT_ATOMIC <
> flat<0x3e>, "flat_atomic_fcmpswap", VGPR_32, VReg_64
> @@ -254,7 +256,7 @@ defm FLAT_ATOMIC_FMAX_X2 : FLAT_ATOMIC <
> flat<0x60>, "flat_atomic_fmax_x2", VReg_64
> >;
>
> -} // End SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst
> +} // End SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst,
> DisableVIDecoder = 1
>
> let Predicates = [isCI] in {
>
>
> Modified: llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt?rev=261185&r1=261184&r2=261185&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt Wed Feb 17 21:42:32 2016
> @@ -10,6 +10,7 @@ tablegen(LLVM AMDGPUGenMCCodeEmitter.inc
> tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
> tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
> tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
> +tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
> add_public_tablegen_target(AMDGPUCommonTableGen)
>
> add_llvm_target(AMDGPUCodeGen
> @@ -65,6 +66,7 @@ add_llvm_target(AMDGPUCodeGen
>
> add_subdirectory(AsmParser)
> add_subdirectory(InstPrinter)
> +add_subdirectory(Disassembler)
> add_subdirectory(TargetInfo)
> add_subdirectory(MCTargetDesc)
> add_subdirectory(Utils)
>
> Added: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp?rev=261185&view=auto
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
> (added)
> +++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp Wed
> Feb 17 21:42:32 2016
> @@ -0,0 +1,302 @@
> +//===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA
> --------------===//
> +//
> +// The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
>
> +//===----------------------------------------------------------------------===//
> +//
>
> +//===----------------------------------------------------------------------===//
> +//
> +/// \file
> +///
> +/// This file contains definition for AMDGPU ISA disassembler
> +//
>
> +//===----------------------------------------------------------------------===//
> +
> +// ToDo: What to do with instruction suffixes (v_mov_b32 vs
> v_mov_b32_e32)?
> +
> +#include "AMDGPUDisassembler.h"
> +#include "AMDGPU.h"
> +#include "AMDGPURegisterInfo.h"
> +#include "Utils/AMDGPUBaseInfo.h"
> +
> +#include "llvm/MC/MCFixedLenDisassembler.h"
> +#include "llvm/MC/MCInst.h"
> +#include "llvm/MC/MCInstrDesc.h"
> +#include "llvm/MC/MCSubtargetInfo.h"
> +#include "llvm/Support/Debug.h"
> +#include "llvm/Support/TargetRegistry.h"
> +
> +
> +using namespace llvm;
> +
> +#define DEBUG_TYPE "amdgpu-disassembler"
> +
> +typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
> +
> +
> +static DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
> + uint64_t Addr, const void
> *Decoder) {
> + const AMDGPUDisassembler *Dis =
> + static_cast<const AMDGPUDisassembler *>(Decoder);
> + return Dis->DecodeVGPR_32RegisterClass(Inst, Imm, Addr);
> +}
> +
> +static DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
> + uint64_t Addr, const void
> *Decoder) {
> + const AMDGPUDisassembler *Dis =
> + static_cast<const AMDGPUDisassembler *>(Decoder);
> + return Dis->DecodeVS_32RegisterClass(Inst, Imm, Addr);
> +}
> +
> +static DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
> + uint64_t Addr, const void
> *Decoder) {
> + // ToDo
> + return MCDisassembler::Fail;
> +}
> +
> +static DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
> + uint64_t Addr, const void
> *Decoder) {
> + // ToDo
> + return MCDisassembler::Fail;
> +}
> +
> +static DecodeStatus DecodeVReg_96RegisterClass(MCInst &Inst, unsigned Imm,
> + uint64_t Addr, const void
> *Decoder) {
> + // ToDo
> + return MCDisassembler::Fail;
> +}
> +
> +static DecodeStatus DecodeVReg_128RegisterClass(MCInst &Inst, unsigned
> Imm,
> + uint64_t Addr, const void
> *Decoder) {
> + // ToDo
> + return MCDisassembler::Fail;
> +}
> +
> +static DecodeStatus DecodeSReg_32RegisterClass(MCInst &Inst, unsigned Imm,
> + uint64_t Addr, const void
> *Decoder) {
> + // ToDo
> + return MCDisassembler::Fail;
> +}
> +
> +static DecodeStatus DecodeSReg_64RegisterClass(MCInst &Inst, unsigned Imm,
> + uint64_t Addr, const void
> *Decoder) {
> + // ToDo
> + return MCDisassembler::Fail;
> +}
> +
> +static DecodeStatus DecodeSReg_128RegisterClass(MCInst &Inst, unsigned
> Imm,
> + uint64_t Addr, const void
> *Decoder) {
> + // ToDo
> + return MCDisassembler::Fail;
> +}
> +
> +static DecodeStatus DecodeSReg_256RegisterClass(MCInst &Inst, unsigned
> Imm,
> + uint64_t Addr, const void
> *Decoder) {
> + // ToDo
> + return MCDisassembler::Fail;
> +}
> +
> +
> +#define GET_SUBTARGETINFO_ENUM
> +#include "AMDGPUGenSubtargetInfo.inc"
> +#undef GET_SUBTARGETINFO_ENUM
> +
> +#include "AMDGPUGenDisassemblerTables.inc"
> +
>
> +//===----------------------------------------------------------------------===//
> +//
>
> +//===----------------------------------------------------------------------===//
> +
> +DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t
> &Size,
> + ArrayRef<uint8_t> Bytes,
> + uint64_t Address,
> + raw_ostream &WS,
> + raw_ostream &CS) const {
> + CommentStream = &CS;
> +
> + // ToDo: AMDGPUDisassembler supports only VI ISA.
> + assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
> +
> + // Try decode 32-bit instruction
> + if (Bytes.size() < 4) {
> + Size = 0;
> + return MCDisassembler::Fail;
> + }
> + uint32_t Insn =
> + (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0]
> << 0);
> +
> + // Calling the auto-generated decoder function.
> + DecodeStatus Result =
> + decodeInstruction(DecoderTableVI32, MI, Insn, Address, this, STI);
> + if (Result != MCDisassembler::Success) {
> + Size = 0;
> + return MCDisassembler::Fail;
> + }
> + Size = 4;
> +
> + return MCDisassembler::Success;
> +}
> +
> +DecodeStatus AMDGPUDisassembler::DecodeLitFloat(unsigned Imm, uint32_t&
> F) const {
> + // ToDo: case 248: 1/(2*PI) - is allowed only on VI
> + // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider
> 1/(2*PI) as
> + // literal constant.
> + switch(Imm) {
> + case 240: F = FloatToBits(0.5f); return MCDisassembler::Success;
> + case 241: F = FloatToBits(-0.5f); return MCDisassembler::Success;
> + case 242: F = FloatToBits(1.0f); return MCDisassembler::Success;
> + case 243: F = FloatToBits(-1.0f); return MCDisassembler::Success;
> + case 244: F = FloatToBits(2.0f); return MCDisassembler::Success;
> + case 245: F = FloatToBits(-2.0f); return MCDisassembler::Success;
> + case 246: F = FloatToBits(4.0f); return MCDisassembler::Success;
> + case 247: F = FloatToBits(-4.0f); return MCDisassembler::Success;
> + case 248: F = 0x3e22f983; return MCDisassembler::Success; // 1/(2*PI)
> + default: return MCDisassembler::Fail;
> + }
> +}
> +
> +DecodeStatus AMDGPUDisassembler::DecodeLitInteger(unsigned Imm,
> + int64_t& I) const {
> + if ((Imm >= 128) && (Imm <= 192)) {
> + I = Imm - 128;
> + return MCDisassembler::Success;
> + } else if ((Imm >= 193) && (Imm <= 208)) {
> + I = 192 - Imm;
> + return MCDisassembler::Success;
> + }
> + return MCDisassembler::Fail;
> +}
> +
> +DecodeStatus AMDGPUDisassembler::DecodeVgprRegister(unsigned Val,
> + unsigned& RegID)
> const {
> + if (Val > 255) {
> + return MCDisassembler::Fail;
> + }
> + RegID =
> AMDGPUMCRegisterClasses[AMDGPU::VGPR_32RegClassID].getRegister(Val);
> + return MCDisassembler::Success;
> +}
> +
> +DecodeStatus AMDGPUDisassembler::DecodeSgprRegister(unsigned Val,
> + unsigned& RegID)
> const {
> + // ToDo: SI/CI have 104 SGPRs, VI - 102
> + if (Val > 101) {
> + return MCDisassembler::Fail;
> + }
> + RegID =
> AMDGPUMCRegisterClasses[AMDGPU::SGPR_32RegClassID].getRegister(Val);
> + return MCDisassembler::Success;
> +}
> +
> +DecodeStatus AMDGPUDisassembler::DecodeSrcRegister(unsigned Val,
> + unsigned& RegID) const
> {
> + // ToDo: deal with out-of range registers
> + using namespace AMDGPU;
> + if (Val <= 101) {
> + return DecodeSgprRegister(Val, RegID);
> + } else if ((Val >= 256) && (Val <= 511)) {
> + return DecodeVgprRegister(Val - 256, RegID);
> + } else {
> + switch(Val) {
> + case 102: RegID = getMCReg(FLAT_SCR_LO, STI); return
> MCDisassembler::Success;
> + case 103: RegID = getMCReg(FLAT_SCR_HI, STI); return
> MCDisassembler::Success;
> + // ToDo: no support for xnack_mask_lo/_hi register
> + case 104:
> + case 105: return MCDisassembler::Fail;
> + case 106: RegID = getMCReg(VCC_LO, STI); return
> MCDisassembler::Success;
> + case 107: RegID = getMCReg(VCC_HI, STI); return
> MCDisassembler::Success;
> + // ToDo: no support for tba_lo/_hi register
> + case 108:
> + case 109: return MCDisassembler::Fail;
> + // ToDo: no support for tma_lo/_hi register
> + case 110:
> + case 111: return MCDisassembler::Fail;
> + // ToDo: no support for ttmp[0:11] register
> + case 112:
> + case 113:
> + case 114:
> + case 115:
> + case 116:
> + case 117:
> + case 118:
> + case 119:
> + case 120:
> + case 121:
> + case 122:
> + case 123: return MCDisassembler::Fail;
> + case 124: RegID = getMCReg(M0, STI); return MCDisassembler::Success;
> + case 126: RegID = getMCReg(EXEC_LO, STI); return
> MCDisassembler::Success;
> + case 127: RegID = getMCReg(EXEC_HI, STI); return
> MCDisassembler::Success;
> + // ToDo: no support for vccz register
> + case 251: return MCDisassembler::Fail;
> + // ToDo: no support for execz register
> + case 252: return MCDisassembler::Fail;
> + case 253: RegID = getMCReg(SCC, STI); return MCDisassembler::Success;
> + default: return MCDisassembler::Fail;
> + }
> + }
> + return MCDisassembler::Fail;
> +}
> +
> +DecodeStatus AMDGPUDisassembler::DecodeVGPR_32RegisterClass(llvm::MCInst
> &Inst,
> + unsigned Imm,
> + uint64_t
> Addr) const {
> + unsigned RegID;
> + if (DecodeVgprRegister(Imm, RegID) == MCDisassembler::Success) {
> + Inst.addOperand(MCOperand::createReg(RegID));
> + return MCDisassembler::Success;
> + }
> + return MCDisassembler::Fail;
> +}
> +
> +DecodeStatus AMDGPUDisassembler::DecodeVS_32RegisterClass(MCInst &Inst,
> + unsigned Imm,
> + uint64_t Addr)
> const {
> + // ToDo: different opcodes allow different formats og this operands
> + if ((Imm >= 128) && (Imm <= 208)) {
> + // immediate integer
> + int64_t Val;
> + if (DecodeLitInteger(Imm, Val) == MCDisassembler::Success) {
> + Inst.addOperand(MCOperand::createImm(Val));
> + return MCDisassembler::Success;
> + }
> + } else if ((Imm >= 240) && (Imm <= 248)) {
> + // immediate float
> + uint32_t Val;
> + if (DecodeLitFloat(Imm, Val) == MCDisassembler::Success) {
> + Inst.addOperand(MCOperand::createImm(Val));
> + return MCDisassembler::Success;
> + }
> + } else if (Imm == 254) {
> + // LDS direct
> + // ToDo: implement LDS direct read
> + } else if (Imm == 255) {
> + // literal constant
> + } else if ((Imm == 125) ||
> + ((Imm >= 209) && (Imm <= 239)) ||
> + (Imm == 249) ||
> + (Imm == 250) ||
> + (Imm >= 512)) {
> + // reserved
> + return MCDisassembler::Fail;
> + } else {
> + // register
> + unsigned RegID;
> + if (DecodeSrcRegister(Imm, RegID) == MCDisassembler::Success) {
> + Inst.addOperand(MCOperand::createReg(RegID));
> + return MCDisassembler::Success;
> + }
> + }
> + return MCDisassembler::Fail;
> +}
> +
> +static MCDisassembler *createAMDGPUDisassembler(const Target &T,
> + const MCSubtargetInfo
> &STI,
> + MCContext &Ctx) {
> + return new AMDGPUDisassembler(STI, Ctx);
> +}
> +
> +extern "C" void LLVMInitializeAMDGPUDisassembler() {
> + TargetRegistry::RegisterMCDisassembler(TheGCNTarget,
> createAMDGPUDisassembler);
> +}
>
> Added: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h?rev=261185&view=auto
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h (added)
> +++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h Wed Feb
> 17 21:42:32 2016
> @@ -0,0 +1,57 @@
> +//===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++
> -*--===//
> +//
> +// The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
>
> +//===----------------------------------------------------------------------===//
> +//
> +/// \file
> +///
> +/// This file contains declaration for AMDGPU ISA disassembler
> +//
>
> +//===----------------------------------------------------------------------===//
> +
> +#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
> +#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
> +
> +#include "llvm/MC/MCDisassembler/MCDisassembler.h"
> +
> +namespace llvm {
> +
> + class MCContext;
> + class MCInst;
> + class MCSubtargetInfo;
> +
> + class AMDGPUDisassembler : public MCDisassembler {
> + public:
> + AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
> + MCDisassembler(STI, Ctx) {}
> +
> + ~AMDGPUDisassembler() {}
> +
> + DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
> + ArrayRef<uint8_t> Bytes, uint64_t Address,
> + raw_ostream &WS, raw_ostream &CS) const
> override;
> +
> + /// Decode inline float value in VSrc field
> + DecodeStatus DecodeLitFloat(unsigned Imm, uint32_t& F) const;
> + /// Decode inline integer value in VSrc field
> + DecodeStatus DecodeLitInteger(unsigned Imm, int64_t& I) const;
> + /// Decode VGPR register
> + DecodeStatus DecodeVgprRegister(unsigned Val, unsigned& RegID) const;
> + /// Decode SGPR register
> + DecodeStatus DecodeSgprRegister(unsigned Val, unsigned& RegID) const;
> + /// Decode register in VSrc field
> + DecodeStatus DecodeSrcRegister(unsigned Val, unsigned& RegID) const;
> +
> + DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
> + uint64_t Addr) const;
> +
> + DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
> + uint64_t Addr) const;
> + };
> +} // namespace llvm
> +
> +#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
>
> Added: llvm/trunk/lib/Target/AMDGPU/Disassembler/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/CMakeLists.txt?rev=261185&view=auto
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/Disassembler/CMakeLists.txt (added)
> +++ llvm/trunk/lib/Target/AMDGPU/Disassembler/CMakeLists.txt Wed Feb 17
> 21:42:32 2016
> @@ -0,0 +1,7 @@
> +include_directories( ${CMAKE_CURRENT_BINARY_DIR}/..
> ${CMAKE_CURRENT_SOURCE_DIR}/.. )
> +
> +add_llvm_library(LLVMAMDGPUDisassembler
> + AMDGPUDisassembler.cpp
> + )
> +
> +add_dependencies(LLVMAMDGPUDisassembler AMDGPUCommonTableGen)
>
> Copied: llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt (from
> r261176, llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt)
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt?p2=llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt&p1=llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt&r1=261176&r2=261185&rev=261185&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt (original)
> +++ llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt Wed Feb 17
> 21:42:32 2016
> @@ -1,4 +1,4 @@
> -;===- ./lib/Target/AMDGPU/LLVMBuild.txt ------------------------*- Conf
> -*--===;
> +;===- ./lib/Target/AMDGPU/Disassembler/LLVMBuild.txt ------------*- Conf
> -*--===;
> ;
> ; The LLVM Compiler Infrastructure
> ;
> @@ -15,19 +15,9 @@
> ;
>
> ;===------------------------------------------------------------------------===;
>
> -[common]
> -subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo Utils
> -
> [component_0]
> -type = TargetGroup
> -name = AMDGPU
> -parent = Target
> -has_asmparser = 1
> -has_asmprinter = 1
> -
> -[component_1]
> type = Library
> -name = AMDGPUCodeGen
> +name = AMDGPUDisassembler
> parent = AMDGPU
> -required_libraries = Analysis AsmPrinter CodeGen Core IPO MC
> AMDGPUAsmParser AMDGPUAsmPrinter AMDGPUDesc AMDGPUInfo AMDGPUUtils Scalar
> SelectionDAG Support Target TransformUtils
> +required_libraries = AMDGPUDesc AMDGPUInfo AMDGPUUtils MC MCDisassembler
> Support
> add_to_library_groups = AMDGPU
>
> Modified: llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt?rev=261185&r1=261184&r2=261185&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt (original)
> +++ llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt Wed Feb 17 21:42:32 2016
> @@ -16,7 +16,7 @@
>
> ;===------------------------------------------------------------------------===;
>
> [common]
> -subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo Utils
> +subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc
> TargetInfo Utils
>
> [component_0]
> type = TargetGroup
> @@ -24,6 +24,7 @@ name = AMDGPU
> parent = Target
> has_asmparser = 1
> has_asmprinter = 1
> +has_disassembler = 1
>
> [component_1]
> type = Library
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td?rev=261185&r1=261184&r2=261185&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td Wed Feb 17 21:42:32 2016
> @@ -75,6 +75,12 @@ class InstSI <dag outs, dag ins, string
> let TSFlags{22} = VOPAsmPrefer32Bit;
>
> let SchedRW = [Write32Bit];
> +
> + field bits<1> DisableSIDecoder = 0;
> + field bits<1> DisableVIDecoder = 0;
> + field bits<1> DisableDecoder = 0;
> +
> + let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
> }
>
> class Enc32 {
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=261185&r1=261184&r2=261185&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Wed Feb 17 21:42:32 2016
> @@ -704,9 +704,15 @@ multiclass EXP_m {
> def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
> }
>
> - def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
> + def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe {
> + let DecoderNamespace="SICI";
> + let DisableDecoder = DisableSIDecoder;
> + }
>
> - def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
> + def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi {
> + let DecoderNamespace="VI";
> + let DisableDecoder = DisableVIDecoder;
> + }
> }
>
>
> //===----------------------------------------------------------------------===//
> @@ -726,6 +732,8 @@ class SOP1_Real_si <sop1 op, string opNa
> SIMCInstr<opName, SISubtarget.SI> {
> let isCodeGenOnly = 0;
> let AssemblerPredicates = [isSICI];
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string
> asm> :
> @@ -734,6 +742,8 @@ class SOP1_Real_vi <sop1 op, string opNa
> SIMCInstr<opName, SISubtarget.VI> {
> let isCodeGenOnly = 0;
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> }
>
> multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
> @@ -812,6 +822,8 @@ class SOP2_Real_si<sop2 op, string opNam
> SOP2e<op.SI>,
> SIMCInstr<opName, SISubtarget.SI> {
> let AssemblerPredicates = [isSICI];
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm>
> :
> @@ -819,6 +831,8 @@ class SOP2_Real_vi<sop2 op, string opNam
> SOP2e<op.VI>,
> SIMCInstr<opName, SISubtarget.VI> {
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> }
>
> multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
> @@ -873,6 +887,8 @@ class SOPK_Real_si <sopk op, string opNa
> SOPKe <op.SI>,
> SIMCInstr<opName, SISubtarget.SI> {
> let AssemblerPredicates = [isSICI];
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> let isCodeGenOnly = 0;
> }
>
> @@ -881,6 +897,8 @@ class SOPK_Real_vi <sopk op, string opNa
> SOPKe <op.VI>,
> SIMCInstr<opName, SISubtarget.VI> {
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> let isCodeGenOnly = 0;
> }
>
> @@ -937,6 +955,8 @@ multiclass SOPK_IMM32 <sopk op, string o
> SOPK64e <op.SI>,
> SIMCInstr<opName, SISubtarget.SI> {
> let AssemblerPredicates = [isSICI];
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> let isCodeGenOnly = 0;
> }
>
> @@ -944,6 +964,8 @@ multiclass SOPK_IMM32 <sopk op, string o
> SOPK64e <op.VI>,
> SIMCInstr<opName, SISubtarget.VI> {
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> let isCodeGenOnly = 0;
> }
> }
> @@ -964,6 +986,8 @@ class SMRD_Real_si <bits<5> op, string o
> SMRDe <op, imm>,
> SIMCInstr<opName, SISubtarget.SI> {
> let AssemblerPredicates = [isSICI];
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
> @@ -972,6 +996,8 @@ class SMRD_Real_vi <bits<8> op, string o
> SMEMe_vi <op, imm>,
> SIMCInstr<opName, SISubtarget.VI> {
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> }
>
> multiclass SMRD_m <smrd op, string opName, bit imm, dag outs, dag ins,
> @@ -1027,6 +1053,7 @@ multiclass SMRD_Helper <smrd op, string
> (outs dstClass:$dst), (ins baseClass:$sbase,
> smrd_literal_offset:$offset),
> opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
> let AssemblerPredicates = [isCIOnly];
> + let DecoderNamespace = "CI";
> }
>
> defm _SGPR : SMRD_m <
> @@ -1123,6 +1150,10 @@ class getIns64 <RegisterOperand Src0RC,
> bit HasModifiers> {
>
> dag ret =
> + !if (!eq(NumSrcArgs, 0),
> + // VOP1 without input operands (V_NOP, V_CLREXCP)
> + (ins),
> + /* else */
> !if (!eq(NumSrcArgs, 1),
> !if (!eq(HasModifiers, 1),
> // VOP1 with modifiers
> @@ -1152,7 +1183,7 @@ class getIns64 <RegisterOperand Src0RC,
> /* else */,
> // VOP3 without modifiers
> (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
> - /* endif */ )));
> + /* endif */ ))));
> }
>
> class getInsDPP <RegisterClass Src0RC, RegisterClass Src1RC, int
> NumSrcArgs,
> @@ -1465,12 +1496,16 @@ class VOP1_Real_si <string opName, vop1
> VOP1<op.SI, outs, ins, asm, []>,
> SIMCInstr <opName#"_e32", SISubtarget.SI> {
> let AssemblerPredicate = SIAssemblerPredicate;
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string
> asm> :
> VOP1<op.VI, outs, ins, asm, []>,
> SIMCInstr <opName#"_e32", SISubtarget.VI> {
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> }
>
> multiclass VOP1_m <vop1 op, string opName, VOPProfile p, list<dag>
> pattern,
> @@ -1512,12 +1547,16 @@ class VOP2_Real_si <string opName, vop2
> VOP2 <op.SI, outs, ins, opName#asm, []>,
> SIMCInstr <opName#"_e32", SISubtarget.SI> {
> let AssemblerPredicates = [isSICI];
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string
> asm> :
> VOP2 <op.VI, outs, ins, opName#asm, []>,
> SIMCInstr <opName#"_e32", SISubtarget.VI> {
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> }
>
> multiclass VOP2SI_m <vop2 op, string opName, VOPProfile p, list<dag>
> pattern,
> @@ -1582,6 +1621,8 @@ class VOP3_Real_si <bits<9> op, dag outs
> VOP3e <op>,
> SIMCInstr<opName#"_e64", SISubtarget.SI> {
> let AssemblerPredicates = [isSICI];
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string
> opName,
> @@ -1590,6 +1631,8 @@ class VOP3_Real_vi <bits<10> op, dag out
> VOP3e_vi <op>,
> SIMCInstr <opName#"_e64", SISubtarget.VI> {
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> }
>
> class VOP3_C_Real_si <bits<9> op, dag outs, dag ins, string asm, string
> opName,
> @@ -1598,6 +1641,8 @@ class VOP3_C_Real_si <bits<9> op, dag ou
> VOP3ce <op>,
> SIMCInstr<opName#"_e64", SISubtarget.SI> {
> let AssemblerPredicates = [isSICI];
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> class VOP3_C_Real_vi <bits<10> op, dag outs, dag ins, string asm, string
> opName,
> @@ -1606,6 +1651,8 @@ class VOP3_C_Real_vi <bits<10> op, dag o
> VOP3ce_vi <op>,
> SIMCInstr <opName#"_e64", SISubtarget.VI> {
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> }
>
> class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string
> opName,
> @@ -1614,6 +1661,8 @@ class VOP3b_Real_si <bits<9> op, dag out
> VOP3be <op>,
> SIMCInstr<opName#"_e64", SISubtarget.SI> {
> let AssemblerPredicates = [isSICI];
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string
> opName,
> @@ -1622,6 +1671,8 @@ class VOP3b_Real_vi <bits<10> op, dag ou
> VOP3be_vi <op>,
> SIMCInstr <opName#"_e64", SISubtarget.VI> {
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> }
>
> multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag>
> pattern,
> @@ -1737,6 +1788,8 @@ multiclass VOP2SI_3VI_m <vop3 op, string
> def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
> SIMCInstr <opName, SISubtarget.SI> {
> let AssemblerPredicates = [isSICI];
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> def _vi : VOP3Common <outs, ins, asm, []>,
> @@ -1744,6 +1797,8 @@ multiclass VOP2SI_3VI_m <vop3 op, string
> VOP3DisableFields <1, 0, 0>,
> SIMCInstr <opName, SISubtarget.VI> {
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> }
> }
>
> @@ -1879,6 +1934,8 @@ let isCodeGenOnly = 0 in {
> SIMCInstr <opName#"_e32", SISubtarget.SI>,
> VOP2_MADKe <op.SI> {
> let AssemblerPredicates = [isSICI];
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
> @@ -1886,6 +1943,8 @@ let isCodeGenOnly = 0 in {
> SIMCInstr <opName#"_e32", SISubtarget.VI>,
> VOP2_MADKe <op.VI> {
> let AssemblerPredicates = [isVI];
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> }
> } // End isCodeGenOnly = 0
> }
> @@ -1915,6 +1974,8 @@ multiclass VOPC_m <vopc op, dag ins, str
> let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
> let hasSideEffects = DefExec;
> let SchedRW = sched;
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> } // End AssemblerPredicates = [isSICI]
> @@ -1925,6 +1986,8 @@ multiclass VOPC_m <vopc op, dag ins, str
> let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
> let hasSideEffects = DefExec;
> let SchedRW = sched;
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> }
>
> } // End AssemblerPredicates = [isVI]
> @@ -2115,13 +2178,19 @@ class VINTRP_Real_si <bits <2> op, strin
> string asm> :
> VINTRPCommon <outs, ins, asm, []>,
> VINTRPe <op>,
> - SIMCInstr<opName, SISubtarget.SI>;
> + SIMCInstr<opName, SISubtarget.SI> {
> + let DecoderNamespace = "SICI";
> + let DisableDecoder = DisableSIDecoder;
> +}
>
> class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
> string asm> :
> VINTRPCommon <outs, ins, asm, []>,
> VINTRPe_vi <op>,
> - SIMCInstr<opName, SISubtarget.VI>;
> + SIMCInstr<opName, SISubtarget.VI> {
> + let DecoderNamespace = "VI";
> + let DisableDecoder = DisableVIDecoder;
> +}
>
> multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
> list<dag> pattern = []> {
> @@ -2148,12 +2217,17 @@ class DS_Real_si <bits<8> op, string opN
> DSe <op>,
> SIMCInstr <opName, SISubtarget.SI> {
> let isCodeGenOnly = 0;
> + let DecoderNamespace="SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string
> asm> :
> DS <outs, ins, asm, []>,
> DSe_vi <op>,
> - SIMCInstr <opName, SISubtarget.VI>;
> + SIMCInstr <opName, SISubtarget.VI> {
> + let DecoderNamespace="VI";
> + let DisableDecoder = DisableVIDecoder;
> +}
>
> class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins,
> string asm> :
> DS_Real_si <op,opName, outs, ins, asm> {
> @@ -2354,12 +2428,18 @@ class MTBUF_Real_si <bits<3> op, string
> string asm> :
> MTBUF <outs, ins, asm, []>,
> MTBUFe <op>,
> - SIMCInstr<opName, SISubtarget.SI>;
> + SIMCInstr<opName, SISubtarget.SI> {
> + let DecoderNamespace="SICI";
> + let DisableDecoder = DisableSIDecoder;
> +}
>
> class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string
> asm> :
> MTBUF <outs, ins, asm, []>,
> MTBUFe_vi <op>,
> - SIMCInstr <opName, SISubtarget.VI>;
> + SIMCInstr <opName, SISubtarget.VI> {
> + let DecoderNamespace="VI";
> + let DisableDecoder = DisableVIDecoder;
> +}
>
> multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string
> asm,
> list<dag> pattern> {
> @@ -2450,6 +2530,8 @@ class MUBUF_Real_si <mubuf op, string op
> MUBUFe <op.SI>,
> SIMCInstr<opName, SISubtarget.SI> {
> let lds = 0;
> + let DecoderNamespace="SICI";
> + let DisableDecoder = DisableSIDecoder;
> }
>
> class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
> @@ -2458,6 +2540,8 @@ class MUBUF_Real_vi <mubuf op, string op
> MUBUFe_vi <op.VI>,
> SIMCInstr<opName, SISubtarget.VI> {
> let lds = 0;
> + let DecoderNamespace="VI";
> + let DisableDecoder = DisableVIDecoder;
> }
>
> multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string
> asm,
> @@ -2721,12 +2805,15 @@ class FLAT_Real_ci <bits<7> op, string o
> FLAT <op, outs, ins, asm, []>,
> SIMCInstr<opName, SISubtarget.SI> {
> let AssemblerPredicate = isCIOnly;
> + let DecoderNamespace="CI";
> }
>
> class FLAT_Real_vi <bits<7> op, string opName, dag outs, dag ins, string
> asm> :
> FLAT <op, outs, ins, asm, []>,
> SIMCInstr<opName, SISubtarget.VI> {
> let AssemblerPredicate = VIAssemblerPredicate;
> + let DecoderNamespace="VI";
> + let DisableDecoder = DisableVIDecoder;
> }
>
> multiclass FLAT_AtomicRet_m <flat op, dag outs, dag ins, string asm,
> @@ -2807,9 +2894,19 @@ class MIMG_Mask <string op, int channels
> int Channels = channels;
> }
>
> +class MIMG_Helper <bits<7> op, dag outs, dag ins, string asm,
> + string dns=""> : MIMG<op, outs, ins, asm,[]> {
> + let mayLoad = 1;
> + let mayStore = 0;
> + let hasPostISelHook = 1;
> + let DecoderNamespace = dns;
> + let isAsmParserOnly = !if(!eq(dns,""), 1, 0);
> +}
> +
> class MIMG_NoSampler_Helper <bits<7> op, string asm,
> RegisterClass dst_rc,
> - RegisterClass src_rc> : MIMG <
> + RegisterClass src_rc,
> + string dns=""> : MIMG_Helper <
> op,
> (outs dst_rc:$vdata),
> (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
> @@ -2817,17 +2914,15 @@ class MIMG_NoSampler_Helper <bits<7> op,
> SReg_256:$srsrc),
> asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
> #" $tfe, $lwe, $slc, $vaddr, $srsrc",
> - []> {
> + dns> {
> let ssamp = 0;
> - let mayLoad = 1;
> - let mayStore = 0;
> - let hasPostISelHook = 1;
> }
>
> multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
> RegisterClass dst_rc,
> int channels> {
> - def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
> + def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
> + !if(!eq(channels, 1), "AMDGPU", "")>,
> MIMG_Mask<asm#"_V1", channels>;
> def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
> MIMG_Mask<asm#"_V2", channels>;
> @@ -2844,7 +2939,9 @@ multiclass MIMG_NoSampler <bits<7> op, s
>
> class MIMG_Sampler_Helper <bits<7> op, string asm,
> RegisterClass dst_rc,
> - RegisterClass src_rc, int wqm> : MIMG <
> + RegisterClass src_rc,
> + int wqm,
> + string dns=""> : MIMG_Helper <
> op,
> (outs dst_rc:$vdata),
> (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
> @@ -2852,17 +2949,15 @@ class MIMG_Sampler_Helper <bits<7> op, s
> SReg_256:$srsrc, SReg_128:$ssamp),
> asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
> #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
> - []> {
> - let mayLoad = 1;
> - let mayStore = 0;
> - let hasPostISelHook = 1;
> + dns> {
> let WQM = wqm;
> }
>
> multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
> RegisterClass dst_rc,
> int channels, int wqm> {
> - def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
> + def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm,
> + !if(!eq(channels, 1), "AMDGPU", "")>,
> MIMG_Mask<asm#"_V1", channels>;
> def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
> MIMG_Mask<asm#"_V2", channels>;
> @@ -2874,19 +2969,14 @@ multiclass MIMG_Sampler_Src_Helper <bits
> MIMG_Mask<asm#"_V16", channels>;
> }
>
> -multiclass MIMG_Sampler <bits<7> op, string asm> {
> - defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
> - defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
> - defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
> - defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
> +multiclass MIMG_Sampler <bits<7> op, string asm, int wqm=0> {
> + defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, wqm>;
> + defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, wqm>;
> + defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, wqm>;
> + defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, wqm>;
> }
>
> -multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
> - defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
> - defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
> - defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
> - defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
> -}
> +multiclass MIMG_Sampler_WQM <bits<7> op, string asm> : MIMG_Sampler<op,
> asm, 1>;
>
> class MIMG_Gather_Helper <bits<7> op, string asm,
> RegisterClass dst_rc,
> @@ -2912,6 +3002,8 @@ class MIMG_Gather_Helper <bits<7> op, st
> let MIMG = 0;
> let hasPostISelHook = 0;
> let WQM = wqm;
> +
> + let isAsmParserOnly = 1; // TBD: fix it later
> }
>
> multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
> @@ -2929,19 +3021,14 @@ multiclass MIMG_Gather_Src_Helper <bits<
> MIMG_Mask<asm#"_V16", channels>;
> }
>
> -multiclass MIMG_Gather <bits<7> op, string asm> {
> - defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
> - defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
> - defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
> - defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
> +multiclass MIMG_Gather <bits<7> op, string asm, int wqm=0> {
> + defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, wqm>;
> + defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, wqm>;
> + defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, wqm>;
> + defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, wqm>;
> }
>
> -multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
> - defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
> - defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
> - defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
> - defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
> -}
> +multiclass MIMG_Gather_WQM <bits<7> op, string asm> : MIMG_Gather<op,
> asm, 1>;
>
>
> //===----------------------------------------------------------------------===//
> // Vector instruction mappings
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=261185&r1=261184&r2=261185&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Wed Feb 17 21:42:32 2016
> @@ -1034,7 +1034,7 @@ defm BUFFER_ATOMIC_XOR : MUBUF_Atomic <
> //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>,
> "buffer_atomic_fmin_x2", []>; // isn't on VI
> //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>,
> "buffer_atomic_fmax_x2", []>; // isn't on VI
>
> -let SubtargetPredicate = isSI in {
> +let SubtargetPredicate = isSI, DisableVIDecoder = 1 in {
> defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>,
> "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI
> }
>
> @@ -1396,11 +1396,11 @@ defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m
>
> } // End OtherPredicates = [has32BankLDS]
>
> -let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst"
> in {
> +let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst",
> isAsmParserOnly=1 in {
>
> defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
>
> -} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber
> $dst"
> +} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber
> $dst", isAsmParserOnly=1
>
> let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {
>
> @@ -1759,9 +1759,12 @@ defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a
> VOP_I32_I32_I32, mulhu
> >;
>
> +let DisableVIDecoder=1 in { // removed from VI as identical to
> V_MUL_LO_U32
> defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",
> VOP_I32_I32_I32
> >;
> +}
> +
> defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
> VOP_I32_I32_I32, mulhs
> >;
> @@ -1830,7 +1833,7 @@ defm V_MULLIT_F32 : VOP3Inst <vop3<0x150
>
> } // End SubtargetPredicate = isSICI
>
> -let SubtargetPredicate = isVI in {
> +let SubtargetPredicate = isVI, DisableSIDecoder = 1 in {
>
> defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64",
> VOP_I64_I32_I64
>
> Modified: llvm/trunk/lib/Target/AMDGPU/VIInstructions.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VIInstructions.td?rev=261185&r1=261184&r2=261185&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/VIInstructions.td (original)
> +++ llvm/trunk/lib/Target/AMDGPU/VIInstructions.td Wed Feb 17 21:42:32 2016
> @@ -11,6 +11,8 @@
>
> let SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI in {
>
> +let DisableSIDecoder = 1 in {
> +
>
> //===----------------------------------------------------------------------===//
> // VOP1 Instructions
>
> //===----------------------------------------------------------------------===//
> @@ -73,6 +75,8 @@ defm V_MIN_I16 : VOP2Inst <vop2<0,0x32>,
> } // End isCommutable = 1
> defm V_LDEXP_F16 : VOP2Inst <vop2<0,0x33>, "v_ldexp_f16",
> VOP_F16_F16_I16>;
>
> +} // let DisableSIDecoder = 1
> +
> // Aliases to simplify matching of floating-point instructions that
> // are VOP2 on SI and VOP3 on VI.
>
>
> Added: llvm/trunk/test/MC/Disassembler/AMDGPU/lit.local.cfg
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/lit.local.cfg?rev=261185&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/AMDGPU/lit.local.cfg (added)
> +++ llvm/trunk/test/MC/Disassembler/AMDGPU/lit.local.cfg Wed Feb 17
> 21:42:32 2016
> @@ -0,0 +1,2 @@
> +if not 'AMDGPU' in config.root.targets:
> + config.unsupported = True
>
> Added: llvm/trunk/test/MC/Disassembler/AMDGPU/mov.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/mov.txt?rev=261185&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/AMDGPU/mov.txt (added)
> +++ llvm/trunk/test/MC/Disassembler/AMDGPU/mov.txt Wed Feb 17 21:42:32 2016
> @@ -0,0 +1,31 @@
> +# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s
> | FileCheck %s
> +
> +# CHECK: v_mov_b32_e32 v2, v1 ; encoding: [0x01,0x03,0x04,0x7e]
> +0x01 0x03 0x04 0x7e
> +
> +# CHECK: v_mov_b32_e32 v1, 0.5 ; encoding: [0xf0,0x02,0x02,0x7e]
> +0xf0 0x02 0x02 0x7e
> +
> +# CHECK: v_mov_b32_e32 v15, s100 ; encoding: [0x64,0x02,0x1e,0x7e]
> +0x64 0x02 0x1e 0x7e
> +
> +# CHECK: v_mov_b32_e32 v90, flat_scratch_lo ; encoding:
> [0x66,0x02,0xb4,0x7e]
> +0x66 0x02 0xb4 0x7e
> +
> +# CHECK: v_mov_b32_e32 v150, vcc_lo ; encoding:
> [0x6a,0x02,0x2c,0x7f]
> +0x6a 0x02 0x2c 0x7f
> +
> +# CHECK: v_mov_b32_e32 v199, exec_lo ; encoding:
> [0x7e,0x02,0x8e,0x7f]
> +0x7e 0x02 0x8e 0x7f
> +
> +# CHECK: v_mov_b32_e32 v222, m0 ; encoding: [0x7c,0x02,0xbc,0x7f]
> +0x7c 0x02 0xbc 0x7f
> +
> +# CHECK: v_mov_b32_e32 v255, -13 ; encoding: [0xcd,0x02,0xfe,0x7f]
> +0xcd 0x02 0xfe 0x7f
> +
> +# CHECK: v_cvt_f32_i32_e32 v153, s98 ; encoding:
> [0x62,0x0a,0x32,0x7f]
> +0x62 0x0a 0x32 0x7f
> +
> +# CHECK: v_cvt_f32_u32_e32 v33, -4.0 ; encoding:
> [0xf7,0x0c,0x42,0x7e]
> +0xf7 0x0c 0x42 0x7e
> \ No newline at end of file
>
> Added: llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt?rev=261185&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt (added)
> +++ llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt Wed Feb 17 21:42:32 2016
> @@ -0,0 +1,4 @@
> +# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s
> | FileCheck %s
> +
> +# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
> +0x00 0x00 0x00 0x7e
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>
--
~Craig
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