<div dir="ltr">The comments here say that Targets.td was modified to support <span style="font-size:12.8px">DecoderMethod=“NONE”, but that doesn't seem to be in the content.</span></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Feb 17, 2016 at 7:42 PM, Tom Stellard via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: tstellar<br>
Date: Wed Feb 17 21:42:32 2016<br>
New Revision: 261185<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=261185&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=261185&view=rev</a><br>
Log:<br>
[AMDGPU] Disassembler: Added basic disassembler for AMDGPU target<br>
<br>
Changes:<br>
<br>
- Added disassembler project<br>
- Fixed all decoding conflicts in .td files<br>
- Added DecoderMethod=“NONE” option to Target.td that allows to<br>
disable decoder generation for an instruction.<br>
- Created decoding functions for VS_32 and VReg_32 register classes.<br>
- Added stubs for decoding all register classes.<br>
- Added several tests for disassembler<br>
<br>
Disassembler only supports:<br>
<br>
- VI subtarget<br>
- VOP1 instruction encoding<br>
- 32-bit register operands and inline constants<br>
<br>
[Valery]<br>
<br>
One of the point that requires to pay attention to is how decoder<br>
conflicts were resolved:<br>
<br>
- Groups of target instructions were separated by using different<br>
DecoderNamespace (SICI, VI, CI) using similar to AssemblerPredicate<br>
approach.<br>
<br>
- There were conflicts in IMAGE_<> instructions caused by two<br>
different reasons:<br>
<br>
1. dmask wasn’t specified for the output (fixed)<br>
2. There are image instructions that differ only by the number of<br>
the address components but have the same encoding by the HW spec. The<br>
actual number of address components is determined by the HW at runtime<br>
using image resource descriptor starting from the VGPR encoded in an<br>
IMAGE instruction. This means that we should choose only one instruction<br>
from conflicting group to be the rule for decoder. I didn’t find the way<br>
to disable decoder generation for an arbitrary instruction and therefore<br>
made a onelinear fix to tablegen generator that would suppress decoder<br>
generation when DecoderMethod is set to “NONE”. This is a change that<br>
should be reviewed and submitted first. Otherwise I would need to<br>
specify different DecoderNamespace for every instruction in the<br>
conflicting group. I haven’t checked yet if DecoderMethod=“NONE” is not<br>
used in other targets.<br>
3. IMAGE_GATHER decoder generation is for now disabled and to be<br>
done later.<br>
<br>
[/Valery]<br>
<br>
Patch By: Sam Kolton<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D16723" rel="noreferrer" target="_blank">http://reviews.llvm.org/D16723</a><br>
<br>
Added:<br>
llvm/trunk/lib/Target/AMDGPU/Disassembler/<br>
llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp<br>
llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h<br>
llvm/trunk/lib/Target/AMDGPU/Disassembler/CMakeLists.txt<br>
llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt<br>
- copied, changed from r261176, llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt<br>
llvm/trunk/test/MC/Disassembler/AMDGPU/<br>
llvm/trunk/test/MC/Disassembler/AMDGPU/lit.local.cfg<br>
llvm/trunk/test/MC/Disassembler/AMDGPU/mov.txt<br>
llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt<br>
Modified:<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td<br>
llvm/trunk/lib/Target/AMDGPU/CIInstructions.td<br>
llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt<br>
llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt<br>
llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td<br>
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td<br>
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td<br>
llvm/trunk/lib/Target/AMDGPU/VIInstructions.td<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=261185&r1=261184&r2=261185&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=261185&r1=261184&r2=261185&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td Wed Feb 17 21:42:32 2016<br>
@@ -23,6 +23,14 @@ class AMDGPUInst <dag outs, dag ins, str<br>
let Pattern = pattern;<br>
let Itinerary = NullALU;<br>
<br>
+ // SoftFail is a field the disassembler can use to provide a way for<br>
+ // instructions to not match without killing the whole decode process. It is<br>
+ // mainly used for ARM, but Tablegen expects this field to exist or it fails<br>
+ // to build the decode table.<br>
+ field bits<64> SoftFail = 0;<br>
+<br>
+ let DecoderNamespace = Namespace;<br>
+<br>
let TSFlags{63} = isRegisterLoad;<br>
let TSFlags{62} = isRegisterStore;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/CIInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/CIInstructions.td?rev=261185&r1=261184&r2=261185&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/CIInstructions.td?rev=261185&r1=261184&r2=261185&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/CIInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/CIInstructions.td Wed Feb 17 21:42:32 2016<br>
@@ -100,9 +100,11 @@ defm S_DCACHE_INV_VOL : SMRD_Inval <smrd<br>
// MUBUF Instructions<br>
//===----------------------------------------------------------------------===//<br>
<br>
+let DisableSIDecoder = 1 in {<br>
defm BUFFER_WBINVL1_VOL : MUBUF_Invalidate <mubuf<0x70, 0x3f>,<br>
"buffer_wbinvl1_vol", int_amdgcn_buffer_wbinvl1_vol<br>
>;<br>
+}<br>
<br>
//===----------------------------------------------------------------------===//<br>
// Flat Instructions<br>
@@ -233,7 +235,7 @@ defm FLAT_ATOMIC_DEC_X2 : FLAT_ATOMIC <<br>
<br>
// CI Only flat instructions<br>
<br>
-let SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst in {<br>
+let SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst, DisableVIDecoder = 1 in {<br>
<br>
defm FLAT_ATOMIC_FCMPSWAP : FLAT_ATOMIC <<br>
flat<0x3e>, "flat_atomic_fcmpswap", VGPR_32, VReg_64<br>
@@ -254,7 +256,7 @@ defm FLAT_ATOMIC_FMAX_X2 : FLAT_ATOMIC <<br>
flat<0x60>, "flat_atomic_fmax_x2", VReg_64<br>
>;<br>
<br>
-} // End SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst<br>
+} // End SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst, DisableVIDecoder = 1<br>
<br>
let Predicates = [isCI] in {<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt?rev=261185&r1=261184&r2=261185&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt?rev=261185&r1=261184&r2=261185&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt Wed Feb 17 21:42:32 2016<br>
@@ -10,6 +10,7 @@ tablegen(LLVM AMDGPUGenMCCodeEmitter.inc<br>
tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)<br>
tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)<br>
tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)<br>
+tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)<br>
add_public_tablegen_target(AMDGPUCommonTableGen)<br>
<br>
add_llvm_target(AMDGPUCodeGen<br>
@@ -65,6 +66,7 @@ add_llvm_target(AMDGPUCodeGen<br>
<br>
add_subdirectory(AsmParser)<br>
add_subdirectory(InstPrinter)<br>
+add_subdirectory(Disassembler)<br>
add_subdirectory(TargetInfo)<br>
add_subdirectory(MCTargetDesc)<br>
add_subdirectory(Utils)<br>
<br>
Added: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp?rev=261185&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp?rev=261185&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (added)<br>
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp Wed Feb 17 21:42:32 2016<br>
@@ -0,0 +1,302 @@<br>
+//===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+///<br>
+/// This file contains definition for AMDGPU ISA disassembler<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+// ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?<br>
+<br>
+#include "AMDGPUDisassembler.h"<br>
+#include "AMDGPU.h"<br>
+#include "AMDGPURegisterInfo.h"<br>
+#include "Utils/AMDGPUBaseInfo.h"<br>
+<br>
+#include "llvm/MC/MCFixedLenDisassembler.h"<br>
+#include "llvm/MC/MCInst.h"<br>
+#include "llvm/MC/MCInstrDesc.h"<br>
+#include "llvm/MC/MCSubtargetInfo.h"<br>
+#include "llvm/Support/Debug.h"<br>
+#include "llvm/Support/TargetRegistry.h"<br>
+<br>
+<br>
+using namespace llvm;<br>
+<br>
+#define DEBUG_TYPE "amdgpu-disassembler"<br>
+<br>
+typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;<br>
+<br>
+<br>
+static DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr, const void *Decoder) {<br>
+ const AMDGPUDisassembler *Dis =<br>
+ static_cast<const AMDGPUDisassembler *>(Decoder);<br>
+ return Dis->DecodeVGPR_32RegisterClass(Inst, Imm, Addr);<br>
+}<br>
+<br>
+static DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr, const void *Decoder) {<br>
+ const AMDGPUDisassembler *Dis =<br>
+ static_cast<const AMDGPUDisassembler *>(Decoder);<br>
+ return Dis->DecodeVS_32RegisterClass(Inst, Imm, Addr);<br>
+}<br>
+<br>
+static DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr, const void *Decoder) {<br>
+ // ToDo<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+static DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr, const void *Decoder) {<br>
+ // ToDo<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+static DecodeStatus DecodeVReg_96RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr, const void *Decoder) {<br>
+ // ToDo<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+static DecodeStatus DecodeVReg_128RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr, const void *Decoder) {<br>
+ // ToDo<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+static DecodeStatus DecodeSReg_32RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr, const void *Decoder) {<br>
+ // ToDo<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+static DecodeStatus DecodeSReg_64RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr, const void *Decoder) {<br>
+ // ToDo<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+static DecodeStatus DecodeSReg_128RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr, const void *Decoder) {<br>
+ // ToDo<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+static DecodeStatus DecodeSReg_256RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr, const void *Decoder) {<br>
+ // ToDo<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+<br>
+#define GET_SUBTARGETINFO_ENUM<br>
+#include "AMDGPUGenSubtargetInfo.inc"<br>
+#undef GET_SUBTARGETINFO_ENUM<br>
+<br>
+#include "AMDGPUGenDisassemblerTables.inc"<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,<br>
+ ArrayRef<uint8_t> Bytes,<br>
+ uint64_t Address,<br>
+ raw_ostream &WS,<br>
+ raw_ostream &CS) const {<br>
+ CommentStream = &CS;<br>
+<br>
+ // ToDo: AMDGPUDisassembler supports only VI ISA.<br>
+ assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");<br>
+<br>
+ // Try decode 32-bit instruction<br>
+ if (Bytes.size() < 4) {<br>
+ Size = 0;<br>
+ return MCDisassembler::Fail;<br>
+ }<br>
+ uint32_t Insn =<br>
+ (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);<br>
+<br>
+ // Calling the auto-generated decoder function.<br>
+ DecodeStatus Result =<br>
+ decodeInstruction(DecoderTableVI32, MI, Insn, Address, this, STI);<br>
+ if (Result != MCDisassembler::Success) {<br>
+ Size = 0;<br>
+ return MCDisassembler::Fail;<br>
+ }<br>
+ Size = 4;<br>
+<br>
+ return MCDisassembler::Success;<br>
+}<br>
+<br>
+DecodeStatus AMDGPUDisassembler::DecodeLitFloat(unsigned Imm, uint32_t& F) const {<br>
+ // ToDo: case 248: 1/(2*PI) - is allowed only on VI<br>
+ // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as<br>
+ // literal constant.<br>
+ switch(Imm) {<br>
+ case 240: F = FloatToBits(0.5f); return MCDisassembler::Success;<br>
+ case 241: F = FloatToBits(-0.5f); return MCDisassembler::Success;<br>
+ case 242: F = FloatToBits(1.0f); return MCDisassembler::Success;<br>
+ case 243: F = FloatToBits(-1.0f); return MCDisassembler::Success;<br>
+ case 244: F = FloatToBits(2.0f); return MCDisassembler::Success;<br>
+ case 245: F = FloatToBits(-2.0f); return MCDisassembler::Success;<br>
+ case 246: F = FloatToBits(4.0f); return MCDisassembler::Success;<br>
+ case 247: F = FloatToBits(-4.0f); return MCDisassembler::Success;<br>
+ case 248: F = 0x3e22f983; return MCDisassembler::Success; // 1/(2*PI)<br>
+ default: return MCDisassembler::Fail;<br>
+ }<br>
+}<br>
+<br>
+DecodeStatus AMDGPUDisassembler::DecodeLitInteger(unsigned Imm,<br>
+ int64_t& I) const {<br>
+ if ((Imm >= 128) && (Imm <= 192)) {<br>
+ I = Imm - 128;<br>
+ return MCDisassembler::Success;<br>
+ } else if ((Imm >= 193) && (Imm <= 208)) {<br>
+ I = 192 - Imm;<br>
+ return MCDisassembler::Success;<br>
+ }<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+DecodeStatus AMDGPUDisassembler::DecodeVgprRegister(unsigned Val,<br>
+ unsigned& RegID) const {<br>
+ if (Val > 255) {<br>
+ return MCDisassembler::Fail;<br>
+ }<br>
+ RegID = AMDGPUMCRegisterClasses[AMDGPU::VGPR_32RegClassID].getRegister(Val);<br>
+ return MCDisassembler::Success;<br>
+}<br>
+<br>
+DecodeStatus AMDGPUDisassembler::DecodeSgprRegister(unsigned Val,<br>
+ unsigned& RegID) const {<br>
+ // ToDo: SI/CI have 104 SGPRs, VI - 102<br>
+ if (Val > 101) {<br>
+ return MCDisassembler::Fail;<br>
+ }<br>
+ RegID = AMDGPUMCRegisterClasses[AMDGPU::SGPR_32RegClassID].getRegister(Val);<br>
+ return MCDisassembler::Success;<br>
+}<br>
+<br>
+DecodeStatus AMDGPUDisassembler::DecodeSrcRegister(unsigned Val,<br>
+ unsigned& RegID) const {<br>
+ // ToDo: deal with out-of range registers<br>
+ using namespace AMDGPU;<br>
+ if (Val <= 101) {<br>
+ return DecodeSgprRegister(Val, RegID);<br>
+ } else if ((Val >= 256) && (Val <= 511)) {<br>
+ return DecodeVgprRegister(Val - 256, RegID);<br>
+ } else {<br>
+ switch(Val) {<br>
+ case 102: RegID = getMCReg(FLAT_SCR_LO, STI); return MCDisassembler::Success;<br>
+ case 103: RegID = getMCReg(FLAT_SCR_HI, STI); return MCDisassembler::Success;<br>
+ // ToDo: no support for xnack_mask_lo/_hi register<br>
+ case 104:<br>
+ case 105: return MCDisassembler::Fail;<br>
+ case 106: RegID = getMCReg(VCC_LO, STI); return MCDisassembler::Success;<br>
+ case 107: RegID = getMCReg(VCC_HI, STI); return MCDisassembler::Success;<br>
+ // ToDo: no support for tba_lo/_hi register<br>
+ case 108:<br>
+ case 109: return MCDisassembler::Fail;<br>
+ // ToDo: no support for tma_lo/_hi register<br>
+ case 110:<br>
+ case 111: return MCDisassembler::Fail;<br>
+ // ToDo: no support for ttmp[0:11] register<br>
+ case 112:<br>
+ case 113:<br>
+ case 114:<br>
+ case 115:<br>
+ case 116:<br>
+ case 117:<br>
+ case 118:<br>
+ case 119:<br>
+ case 120:<br>
+ case 121:<br>
+ case 122:<br>
+ case 123: return MCDisassembler::Fail;<br>
+ case 124: RegID = getMCReg(M0, STI); return MCDisassembler::Success;<br>
+ case 126: RegID = getMCReg(EXEC_LO, STI); return MCDisassembler::Success;<br>
+ case 127: RegID = getMCReg(EXEC_HI, STI); return MCDisassembler::Success;<br>
+ // ToDo: no support for vccz register<br>
+ case 251: return MCDisassembler::Fail;<br>
+ // ToDo: no support for execz register<br>
+ case 252: return MCDisassembler::Fail;<br>
+ case 253: RegID = getMCReg(SCC, STI); return MCDisassembler::Success;<br>
+ default: return MCDisassembler::Fail;<br>
+ }<br>
+ }<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+DecodeStatus AMDGPUDisassembler::DecodeVGPR_32RegisterClass(llvm::MCInst &Inst,<br>
+ unsigned Imm,<br>
+ uint64_t Addr) const {<br>
+ unsigned RegID;<br>
+ if (DecodeVgprRegister(Imm, RegID) == MCDisassembler::Success) {<br>
+ Inst.addOperand(MCOperand::createReg(RegID));<br>
+ return MCDisassembler::Success;<br>
+ }<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+DecodeStatus AMDGPUDisassembler::DecodeVS_32RegisterClass(MCInst &Inst,<br>
+ unsigned Imm,<br>
+ uint64_t Addr) const {<br>
+ // ToDo: different opcodes allow different formats og this operands<br>
+ if ((Imm >= 128) && (Imm <= 208)) {<br>
+ // immediate integer<br>
+ int64_t Val;<br>
+ if (DecodeLitInteger(Imm, Val) == MCDisassembler::Success) {<br>
+ Inst.addOperand(MCOperand::createImm(Val));<br>
+ return MCDisassembler::Success;<br>
+ }<br>
+ } else if ((Imm >= 240) && (Imm <= 248)) {<br>
+ // immediate float<br>
+ uint32_t Val;<br>
+ if (DecodeLitFloat(Imm, Val) == MCDisassembler::Success) {<br>
+ Inst.addOperand(MCOperand::createImm(Val));<br>
+ return MCDisassembler::Success;<br>
+ }<br>
+ } else if (Imm == 254) {<br>
+ // LDS direct<br>
+ // ToDo: implement LDS direct read<br>
+ } else if (Imm == 255) {<br>
+ // literal constant<br>
+ } else if ((Imm == 125) ||<br>
+ ((Imm >= 209) && (Imm <= 239)) ||<br>
+ (Imm == 249) ||<br>
+ (Imm == 250) ||<br>
+ (Imm >= 512)) {<br>
+ // reserved<br>
+ return MCDisassembler::Fail;<br>
+ } else {<br>
+ // register<br>
+ unsigned RegID;<br>
+ if (DecodeSrcRegister(Imm, RegID) == MCDisassembler::Success) {<br>
+ Inst.addOperand(MCOperand::createReg(RegID));<br>
+ return MCDisassembler::Success;<br>
+ }<br>
+ }<br>
+ return MCDisassembler::Fail;<br>
+}<br>
+<br>
+static MCDisassembler *createAMDGPUDisassembler(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
+ MCContext &Ctx) {<br>
+ return new AMDGPUDisassembler(STI, Ctx);<br>
+}<br>
+<br>
+extern "C" void LLVMInitializeAMDGPUDisassembler() {<br>
+ TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler);<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h?rev=261185&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h?rev=261185&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h (added)<br>
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h Wed Feb 17 21:42:32 2016<br>
@@ -0,0 +1,57 @@<br>
+//===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+/// \file<br>
+///<br>
+/// This file contains declaration for AMDGPU ISA disassembler<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H<br>
+#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H<br>
+<br>
+#include "llvm/MC/MCDisassembler/MCDisassembler.h"<br>
+<br>
+namespace llvm {<br>
+<br>
+ class MCContext;<br>
+ class MCInst;<br>
+ class MCSubtargetInfo;<br>
+<br>
+ class AMDGPUDisassembler : public MCDisassembler {<br>
+ public:<br>
+ AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :<br>
+ MCDisassembler(STI, Ctx) {}<br>
+<br>
+ ~AMDGPUDisassembler() {}<br>
+<br>
+ DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,<br>
+ ArrayRef<uint8_t> Bytes, uint64_t Address,<br>
+ raw_ostream &WS, raw_ostream &CS) const override;<br>
+<br>
+ /// Decode inline float value in VSrc field<br>
+ DecodeStatus DecodeLitFloat(unsigned Imm, uint32_t& F) const;<br>
+ /// Decode inline integer value in VSrc field<br>
+ DecodeStatus DecodeLitInteger(unsigned Imm, int64_t& I) const;<br>
+ /// Decode VGPR register<br>
+ DecodeStatus DecodeVgprRegister(unsigned Val, unsigned& RegID) const;<br>
+ /// Decode SGPR register<br>
+ DecodeStatus DecodeSgprRegister(unsigned Val, unsigned& RegID) const;<br>
+ /// Decode register in VSrc field<br>
+ DecodeStatus DecodeSrcRegister(unsigned Val, unsigned& RegID) const;<br>
+<br>
+ DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr) const;<br>
+<br>
+ DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,<br>
+ uint64_t Addr) const;<br>
+ };<br>
+} // namespace llvm<br>
+<br>
+#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H<br>
<br>
Added: llvm/trunk/lib/Target/AMDGPU/Disassembler/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/CMakeLists.txt?rev=261185&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/CMakeLists.txt?rev=261185&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/CMakeLists.txt (added)<br>
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/CMakeLists.txt Wed Feb 17 21:42:32 2016<br>
@@ -0,0 +1,7 @@<br>
+include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )<br>
+<br>
+add_llvm_library(LLVMAMDGPUDisassembler<br>
+ AMDGPUDisassembler.cpp<br>
+ )<br>
+<br>
+add_dependencies(LLVMAMDGPUDisassembler AMDGPUCommonTableGen)<br>
<br>
Copied: llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt (from r261176, llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt)<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt?p2=llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt&p1=llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt&r1=261176&r2=261185&rev=261185&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt?p2=llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt&p1=llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt&r1=261176&r2=261185&rev=261185&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt Wed Feb 17 21:42:32 2016<br>
@@ -1,4 +1,4 @@<br>
-;===- ./lib/Target/AMDGPU/LLVMBuild.txt ------------------------*- Conf -*--===;<br>
+;===- ./lib/Target/AMDGPU/Disassembler/LLVMBuild.txt ------------*- Conf -*--===;<br>
;<br>
; The LLVM Compiler Infrastructure<br>
;<br>
@@ -15,19 +15,9 @@<br>
;<br>
;===------------------------------------------------------------------------===;<br>
<br>
-[common]<br>
-subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo Utils<br>
-<br>
[component_0]<br>
-type = TargetGroup<br>
-name = AMDGPU<br>
-parent = Target<br>
-has_asmparser = 1<br>
-has_asmprinter = 1<br>
-<br>
-[component_1]<br>
type = Library<br>
-name = AMDGPUCodeGen<br>
+name = AMDGPUDisassembler<br>
parent = AMDGPU<br>
-required_libraries = Analysis AsmPrinter CodeGen Core IPO MC AMDGPUAsmParser AMDGPUAsmPrinter AMDGPUDesc AMDGPUInfo AMDGPUUtils Scalar SelectionDAG Support Target TransformUtils<br>
+required_libraries = AMDGPUDesc AMDGPUInfo AMDGPUUtils MC MCDisassembler Support<br>
add_to_library_groups = AMDGPU<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt?rev=261185&r1=261184&r2=261185&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt?rev=261185&r1=261184&r2=261185&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt Wed Feb 17 21:42:32 2016<br>
@@ -16,7 +16,7 @@<br>
;===------------------------------------------------------------------------===;<br>
<br>
[common]<br>
-subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo Utils<br>
+subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils<br>
<br>
[component_0]<br>
type = TargetGroup<br>
@@ -24,6 +24,7 @@ name = AMDGPU<br>
parent = Target<br>
has_asmparser = 1<br>
has_asmprinter = 1<br>
+has_disassembler = 1<br>
<br>
[component_1]<br>
type = Library<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td?rev=261185&r1=261184&r2=261185&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td?rev=261185&r1=261184&r2=261185&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td Wed Feb 17 21:42:32 2016<br>
@@ -75,6 +75,12 @@ class InstSI <dag outs, dag ins, string<br>
let TSFlags{22} = VOPAsmPrefer32Bit;<br>
<br>
let SchedRW = [Write32Bit];<br>
+<br>
+ field bits<1> DisableSIDecoder = 0;<br>
+ field bits<1> DisableVIDecoder = 0;<br>
+ field bits<1> DisableDecoder = 0;<br>
+<br>
+ let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);<br>
}<br>
<br>
class Enc32 {<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=261185&r1=261184&r2=261185&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=261185&r1=261184&r2=261185&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Wed Feb 17 21:42:32 2016<br>
@@ -704,9 +704,15 @@ multiclass EXP_m {<br>
def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;<br>
}<br>
<br>
- def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;<br>
+ def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe {<br>
+ let DecoderNamespace="SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
+ }<br>
<br>
- def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;<br>
+ def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi {<br>
+ let DecoderNamespace="VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
+ }<br>
}<br>
<br>
//===----------------------------------------------------------------------===//<br>
@@ -726,6 +732,8 @@ class SOP1_Real_si <sop1 op, string opNa<br>
SIMCInstr<opName, SISubtarget.SI> {<br>
let isCodeGenOnly = 0;<br>
let AssemblerPredicates = [isSICI];<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :<br>
@@ -734,6 +742,8 @@ class SOP1_Real_vi <sop1 op, string opNa<br>
SIMCInstr<opName, SISubtarget.VI> {<br>
let isCodeGenOnly = 0;<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
<br>
multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,<br>
@@ -812,6 +822,8 @@ class SOP2_Real_si<sop2 op, string opNam<br>
SOP2e<op.SI>,<br>
SIMCInstr<opName, SISubtarget.SI> {<br>
let AssemblerPredicates = [isSICI];<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :<br>
@@ -819,6 +831,8 @@ class SOP2_Real_vi<sop2 op, string opNam<br>
SOP2e<op.VI>,<br>
SIMCInstr<opName, SISubtarget.VI> {<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
<br>
multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,<br>
@@ -873,6 +887,8 @@ class SOPK_Real_si <sopk op, string opNa<br>
SOPKe <op.SI>,<br>
SIMCInstr<opName, SISubtarget.SI> {<br>
let AssemblerPredicates = [isSICI];<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
let isCodeGenOnly = 0;<br>
}<br>
<br>
@@ -881,6 +897,8 @@ class SOPK_Real_vi <sopk op, string opNa<br>
SOPKe <op.VI>,<br>
SIMCInstr<opName, SISubtarget.VI> {<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
let isCodeGenOnly = 0;<br>
}<br>
<br>
@@ -937,6 +955,8 @@ multiclass SOPK_IMM32 <sopk op, string o<br>
SOPK64e <op.SI>,<br>
SIMCInstr<opName, SISubtarget.SI> {<br>
let AssemblerPredicates = [isSICI];<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
let isCodeGenOnly = 0;<br>
}<br>
<br>
@@ -944,6 +964,8 @@ multiclass SOPK_IMM32 <sopk op, string o<br>
SOPK64e <op.VI>,<br>
SIMCInstr<opName, SISubtarget.VI> {<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
let isCodeGenOnly = 0;<br>
}<br>
}<br>
@@ -964,6 +986,8 @@ class SMRD_Real_si <bits<5> op, string o<br>
SMRDe <op, imm>,<br>
SIMCInstr<opName, SISubtarget.SI> {<br>
let AssemblerPredicates = [isSICI];<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,<br>
@@ -972,6 +996,8 @@ class SMRD_Real_vi <bits<8> op, string o<br>
SMEMe_vi <op, imm>,<br>
SIMCInstr<opName, SISubtarget.VI> {<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
<br>
multiclass SMRD_m <smrd op, string opName, bit imm, dag outs, dag ins,<br>
@@ -1027,6 +1053,7 @@ multiclass SMRD_Helper <smrd op, string<br>
(outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),<br>
opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {<br>
let AssemblerPredicates = [isCIOnly];<br>
+ let DecoderNamespace = "CI";<br>
}<br>
<br>
defm _SGPR : SMRD_m <<br>
@@ -1123,6 +1150,10 @@ class getIns64 <RegisterOperand Src0RC,<br>
bit HasModifiers> {<br>
<br>
dag ret =<br>
+ !if (!eq(NumSrcArgs, 0),<br>
+ // VOP1 without input operands (V_NOP, V_CLREXCP)<br>
+ (ins),<br>
+ /* else */<br>
!if (!eq(NumSrcArgs, 1),<br>
!if (!eq(HasModifiers, 1),<br>
// VOP1 with modifiers<br>
@@ -1152,7 +1183,7 @@ class getIns64 <RegisterOperand Src0RC,<br>
/* else */,<br>
// VOP3 without modifiers<br>
(ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)<br>
- /* endif */ )));<br>
+ /* endif */ ))));<br>
}<br>
<br>
class getInsDPP <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,<br>
@@ -1465,12 +1496,16 @@ class VOP1_Real_si <string opName, vop1<br>
VOP1<op.SI, outs, ins, asm, []>,<br>
SIMCInstr <opName#"_e32", SISubtarget.SI> {<br>
let AssemblerPredicate = SIAssemblerPredicate;<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :<br>
VOP1<op.VI, outs, ins, asm, []>,<br>
SIMCInstr <opName#"_e32", SISubtarget.VI> {<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
<br>
multiclass VOP1_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,<br>
@@ -1512,12 +1547,16 @@ class VOP2_Real_si <string opName, vop2<br>
VOP2 <op.SI, outs, ins, opName#asm, []>,<br>
SIMCInstr <opName#"_e32", SISubtarget.SI> {<br>
let AssemblerPredicates = [isSICI];<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :<br>
VOP2 <op.VI, outs, ins, opName#asm, []>,<br>
SIMCInstr <opName#"_e32", SISubtarget.VI> {<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
<br>
multiclass VOP2SI_m <vop2 op, string opName, VOPProfile p, list<dag> pattern,<br>
@@ -1582,6 +1621,8 @@ class VOP3_Real_si <bits<9> op, dag outs<br>
VOP3e <op>,<br>
SIMCInstr<opName#"_e64", SISubtarget.SI> {<br>
let AssemblerPredicates = [isSICI];<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,<br>
@@ -1590,6 +1631,8 @@ class VOP3_Real_vi <bits<10> op, dag out<br>
VOP3e_vi <op>,<br>
SIMCInstr <opName#"_e64", SISubtarget.VI> {<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
<br>
class VOP3_C_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,<br>
@@ -1598,6 +1641,8 @@ class VOP3_C_Real_si <bits<9> op, dag ou<br>
VOP3ce <op>,<br>
SIMCInstr<opName#"_e64", SISubtarget.SI> {<br>
let AssemblerPredicates = [isSICI];<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
class VOP3_C_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,<br>
@@ -1606,6 +1651,8 @@ class VOP3_C_Real_vi <bits<10> op, dag o<br>
VOP3ce_vi <op>,<br>
SIMCInstr <opName#"_e64", SISubtarget.VI> {<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
<br>
class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,<br>
@@ -1614,6 +1661,8 @@ class VOP3b_Real_si <bits<9> op, dag out<br>
VOP3be <op>,<br>
SIMCInstr<opName#"_e64", SISubtarget.SI> {<br>
let AssemblerPredicates = [isSICI];<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,<br>
@@ -1622,6 +1671,8 @@ class VOP3b_Real_vi <bits<10> op, dag ou<br>
VOP3be_vi <op>,<br>
SIMCInstr <opName#"_e64", SISubtarget.VI> {<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
<br>
multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,<br>
@@ -1737,6 +1788,8 @@ multiclass VOP2SI_3VI_m <vop3 op, string<br>
def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,<br>
SIMCInstr <opName, SISubtarget.SI> {<br>
let AssemblerPredicates = [isSICI];<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
def _vi : VOP3Common <outs, ins, asm, []>,<br>
@@ -1744,6 +1797,8 @@ multiclass VOP2SI_3VI_m <vop3 op, string<br>
VOP3DisableFields <1, 0, 0>,<br>
SIMCInstr <opName, SISubtarget.VI> {<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
}<br>
<br>
@@ -1879,6 +1934,8 @@ let isCodeGenOnly = 0 in {<br>
SIMCInstr <opName#"_e32", SISubtarget.SI>,<br>
VOP2_MADKe <op.SI> {<br>
let AssemblerPredicates = [isSICI];<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,<br>
@@ -1886,6 +1943,8 @@ let isCodeGenOnly = 0 in {<br>
SIMCInstr <opName#"_e32", SISubtarget.VI>,<br>
VOP2_MADKe <op.VI> {<br>
let AssemblerPredicates = [isVI];<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
} // End isCodeGenOnly = 0<br>
}<br>
@@ -1915,6 +1974,8 @@ multiclass VOPC_m <vopc op, dag ins, str<br>
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);<br>
let hasSideEffects = DefExec;<br>
let SchedRW = sched;<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
} // End AssemblerPredicates = [isSICI]<br>
@@ -1925,6 +1986,8 @@ multiclass VOPC_m <vopc op, dag ins, str<br>
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);<br>
let hasSideEffects = DefExec;<br>
let SchedRW = sched;<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
<br>
} // End AssemblerPredicates = [isVI]<br>
@@ -2115,13 +2178,19 @@ class VINTRP_Real_si <bits <2> op, strin<br>
string asm> :<br>
VINTRPCommon <outs, ins, asm, []>,<br>
VINTRPe <op>,<br>
- SIMCInstr<opName, SISubtarget.SI>;<br>
+ SIMCInstr<opName, SISubtarget.SI> {<br>
+ let DecoderNamespace = "SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
+}<br>
<br>
class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,<br>
string asm> :<br>
VINTRPCommon <outs, ins, asm, []>,<br>
VINTRPe_vi <op>,<br>
- SIMCInstr<opName, SISubtarget.VI>;<br>
+ SIMCInstr<opName, SISubtarget.VI> {<br>
+ let DecoderNamespace = "VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
+}<br>
<br>
multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,<br>
list<dag> pattern = []> {<br>
@@ -2148,12 +2217,17 @@ class DS_Real_si <bits<8> op, string opN<br>
DSe <op>,<br>
SIMCInstr <opName, SISubtarget.SI> {<br>
let isCodeGenOnly = 0;<br>
+ let DecoderNamespace="SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :<br>
DS <outs, ins, asm, []>,<br>
DSe_vi <op>,<br>
- SIMCInstr <opName, SISubtarget.VI>;<br>
+ SIMCInstr <opName, SISubtarget.VI> {<br>
+ let DecoderNamespace="VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
+}<br>
<br>
class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :<br>
DS_Real_si <op,opName, outs, ins, asm> {<br>
@@ -2354,12 +2428,18 @@ class MTBUF_Real_si <bits<3> op, string<br>
string asm> :<br>
MTBUF <outs, ins, asm, []>,<br>
MTBUFe <op>,<br>
- SIMCInstr<opName, SISubtarget.SI>;<br>
+ SIMCInstr<opName, SISubtarget.SI> {<br>
+ let DecoderNamespace="SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
+}<br>
<br>
class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :<br>
MTBUF <outs, ins, asm, []>,<br>
MTBUFe_vi <op>,<br>
- SIMCInstr <opName, SISubtarget.VI>;<br>
+ SIMCInstr <opName, SISubtarget.VI> {<br>
+ let DecoderNamespace="VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
+}<br>
<br>
multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,<br>
list<dag> pattern> {<br>
@@ -2450,6 +2530,8 @@ class MUBUF_Real_si <mubuf op, string op<br>
MUBUFe <op.SI>,<br>
SIMCInstr<opName, SISubtarget.SI> {<br>
let lds = 0;<br>
+ let DecoderNamespace="SICI";<br>
+ let DisableDecoder = DisableSIDecoder;<br>
}<br>
<br>
class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,<br>
@@ -2458,6 +2540,8 @@ class MUBUF_Real_vi <mubuf op, string op<br>
MUBUFe_vi <op.VI>,<br>
SIMCInstr<opName, SISubtarget.VI> {<br>
let lds = 0;<br>
+ let DecoderNamespace="VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
<br>
multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,<br>
@@ -2721,12 +2805,15 @@ class FLAT_Real_ci <bits<7> op, string o<br>
FLAT <op, outs, ins, asm, []>,<br>
SIMCInstr<opName, SISubtarget.SI> {<br>
let AssemblerPredicate = isCIOnly;<br>
+ let DecoderNamespace="CI";<br>
}<br>
<br>
class FLAT_Real_vi <bits<7> op, string opName, dag outs, dag ins, string asm> :<br>
FLAT <op, outs, ins, asm, []>,<br>
SIMCInstr<opName, SISubtarget.VI> {<br>
let AssemblerPredicate = VIAssemblerPredicate;<br>
+ let DecoderNamespace="VI";<br>
+ let DisableDecoder = DisableVIDecoder;<br>
}<br>
<br>
multiclass FLAT_AtomicRet_m <flat op, dag outs, dag ins, string asm,<br>
@@ -2807,9 +2894,19 @@ class MIMG_Mask <string op, int channels<br>
int Channels = channels;<br>
}<br>
<br>
+class MIMG_Helper <bits<7> op, dag outs, dag ins, string asm,<br>
+ string dns=""> : MIMG<op, outs, ins, asm,[]> {<br>
+ let mayLoad = 1;<br>
+ let mayStore = 0;<br>
+ let hasPostISelHook = 1;<br>
+ let DecoderNamespace = dns;<br>
+ let isAsmParserOnly = !if(!eq(dns,""), 1, 0);<br>
+}<br>
+<br>
class MIMG_NoSampler_Helper <bits<7> op, string asm,<br>
RegisterClass dst_rc,<br>
- RegisterClass src_rc> : MIMG <<br>
+ RegisterClass src_rc,<br>
+ string dns=""> : MIMG_Helper <<br>
op,<br>
(outs dst_rc:$vdata),<br>
(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,<br>
@@ -2817,17 +2914,15 @@ class MIMG_NoSampler_Helper <bits<7> op,<br>
SReg_256:$srsrc),<br>
asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"<br>
#" $tfe, $lwe, $slc, $vaddr, $srsrc",<br>
- []> {<br>
+ dns> {<br>
let ssamp = 0;<br>
- let mayLoad = 1;<br>
- let mayStore = 0;<br>
- let hasPostISelHook = 1;<br>
}<br>
<br>
multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,<br>
RegisterClass dst_rc,<br>
int channels> {<br>
- def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,<br>
+ def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,<br>
+ !if(!eq(channels, 1), "AMDGPU", "")>,<br>
MIMG_Mask<asm#"_V1", channels>;<br>
def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,<br>
MIMG_Mask<asm#"_V2", channels>;<br>
@@ -2844,7 +2939,9 @@ multiclass MIMG_NoSampler <bits<7> op, s<br>
<br>
class MIMG_Sampler_Helper <bits<7> op, string asm,<br>
RegisterClass dst_rc,<br>
- RegisterClass src_rc, int wqm> : MIMG <<br>
+ RegisterClass src_rc,<br>
+ int wqm,<br>
+ string dns=""> : MIMG_Helper <<br>
op,<br>
(outs dst_rc:$vdata),<br>
(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,<br>
@@ -2852,17 +2949,15 @@ class MIMG_Sampler_Helper <bits<7> op, s<br>
SReg_256:$srsrc, SReg_128:$ssamp),<br>
asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"<br>
#" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",<br>
- []> {<br>
- let mayLoad = 1;<br>
- let mayStore = 0;<br>
- let hasPostISelHook = 1;<br>
+ dns> {<br>
let WQM = wqm;<br>
}<br>
<br>
multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,<br>
RegisterClass dst_rc,<br>
int channels, int wqm> {<br>
- def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,<br>
+ def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm,<br>
+ !if(!eq(channels, 1), "AMDGPU", "")>,<br>
MIMG_Mask<asm#"_V1", channels>;<br>
def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,<br>
MIMG_Mask<asm#"_V2", channels>;<br>
@@ -2874,19 +2969,14 @@ multiclass MIMG_Sampler_Src_Helper <bits<br>
MIMG_Mask<asm#"_V16", channels>;<br>
}<br>
<br>
-multiclass MIMG_Sampler <bits<7> op, string asm> {<br>
- defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;<br>
- defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;<br>
- defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;<br>
- defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;<br>
+multiclass MIMG_Sampler <bits<7> op, string asm, int wqm=0> {<br>
+ defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, wqm>;<br>
+ defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, wqm>;<br>
+ defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, wqm>;<br>
+ defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, wqm>;<br>
}<br>
<br>
-multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {<br>
- defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;<br>
- defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;<br>
- defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;<br>
- defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;<br>
-}<br>
+multiclass MIMG_Sampler_WQM <bits<7> op, string asm> : MIMG_Sampler<op, asm, 1>;<br>
<br>
class MIMG_Gather_Helper <bits<7> op, string asm,<br>
RegisterClass dst_rc,<br>
@@ -2912,6 +3002,8 @@ class MIMG_Gather_Helper <bits<7> op, st<br>
let MIMG = 0;<br>
let hasPostISelHook = 0;<br>
let WQM = wqm;<br>
+<br>
+ let isAsmParserOnly = 1; // TBD: fix it later<br>
}<br>
<br>
multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,<br>
@@ -2929,19 +3021,14 @@ multiclass MIMG_Gather_Src_Helper <bits<<br>
MIMG_Mask<asm#"_V16", channels>;<br>
}<br>
<br>
-multiclass MIMG_Gather <bits<7> op, string asm> {<br>
- defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;<br>
- defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;<br>
- defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;<br>
- defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;<br>
+multiclass MIMG_Gather <bits<7> op, string asm, int wqm=0> {<br>
+ defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, wqm>;<br>
+ defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, wqm>;<br>
+ defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, wqm>;<br>
+ defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, wqm>;<br>
}<br>
<br>
-multiclass MIMG_Gather_WQM <bits<7> op, string asm> {<br>
- defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;<br>
- defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;<br>
- defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;<br>
- defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;<br>
-}<br>
+multiclass MIMG_Gather_WQM <bits<7> op, string asm> : MIMG_Gather<op, asm, 1>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
// Vector instruction mappings<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=261185&r1=261184&r2=261185&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=261185&r1=261184&r2=261185&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Wed Feb 17 21:42:32 2016<br>
@@ -1034,7 +1034,7 @@ defm BUFFER_ATOMIC_XOR : MUBUF_Atomic <<br>
//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI<br>
//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI<br>
<br>
-let SubtargetPredicate = isSI in {<br>
+let SubtargetPredicate = isSI, DisableVIDecoder = 1 in {<br>
defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>, "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI<br>
}<br>
<br>
@@ -1396,11 +1396,11 @@ defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m<br>
<br>
} // End OtherPredicates = [has32BankLDS]<br>
<br>
-let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst" in {<br>
+let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 in {<br>
<br>
defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;<br>
<br>
-} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst"<br>
+} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1<br>
<br>
let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {<br>
<br>
@@ -1759,9 +1759,12 @@ defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a<br>
VOP_I32_I32_I32, mulhu<br>
>;<br>
<br>
+let DisableVIDecoder=1 in { // removed from VI as identical to V_MUL_LO_U32<br>
defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",<br>
VOP_I32_I32_I32<br>
>;<br>
+}<br>
+<br>
defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",<br>
VOP_I32_I32_I32, mulhs<br>
>;<br>
@@ -1830,7 +1833,7 @@ defm V_MULLIT_F32 : VOP3Inst <vop3<0x150<br>
<br>
} // End SubtargetPredicate = isSICI<br>
<br>
-let SubtargetPredicate = isVI in {<br>
+let SubtargetPredicate = isVI, DisableSIDecoder = 1 in {<br>
<br>
defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64",<br>
VOP_I64_I32_I64<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/VIInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VIInstructions.td?rev=261185&r1=261184&r2=261185&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VIInstructions.td?rev=261185&r1=261184&r2=261185&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/VIInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/VIInstructions.td Wed Feb 17 21:42:32 2016<br>
@@ -11,6 +11,8 @@<br>
<br>
let SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI in {<br>
<br>
+let DisableSIDecoder = 1 in {<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// VOP1 Instructions<br>
//===----------------------------------------------------------------------===//<br>
@@ -73,6 +75,8 @@ defm V_MIN_I16 : VOP2Inst <vop2<0,0x32>,<br>
} // End isCommutable = 1<br>
defm V_LDEXP_F16 : VOP2Inst <vop2<0,0x33>, "v_ldexp_f16", VOP_F16_F16_I16>;<br>
<br>
+} // let DisableSIDecoder = 1<br>
+<br>
// Aliases to simplify matching of floating-point instructions that<br>
// are VOP2 on SI and VOP3 on VI.<br>
<br>
<br>
Added: llvm/trunk/test/MC/Disassembler/AMDGPU/lit.local.cfg<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/lit.local.cfg?rev=261185&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/lit.local.cfg?rev=261185&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/AMDGPU/lit.local.cfg (added)<br>
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/lit.local.cfg Wed Feb 17 21:42:32 2016<br>
@@ -0,0 +1,2 @@<br>
+if not 'AMDGPU' in config.root.targets:<br>
+ config.unsupported = True<br>
<br>
Added: llvm/trunk/test/MC/Disassembler/AMDGPU/mov.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/mov.txt?rev=261185&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/mov.txt?rev=261185&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/AMDGPU/mov.txt (added)<br>
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/mov.txt Wed Feb 17 21:42:32 2016<br>
@@ -0,0 +1,31 @@<br>
+# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s<br>
+<br>
+# CHECK: v_mov_b32_e32 v2, v1 ; encoding: [0x01,0x03,0x04,0x7e]<br>
+0x01 0x03 0x04 0x7e<br>
+<br>
+# CHECK: v_mov_b32_e32 v1, 0.5 ; encoding: [0xf0,0x02,0x02,0x7e]<br>
+0xf0 0x02 0x02 0x7e<br>
+<br>
+# CHECK: v_mov_b32_e32 v15, s100 ; encoding: [0x64,0x02,0x1e,0x7e]<br>
+0x64 0x02 0x1e 0x7e<br>
+<br>
+# CHECK: v_mov_b32_e32 v90, flat_scratch_lo ; encoding: [0x66,0x02,0xb4,0x7e]<br>
+0x66 0x02 0xb4 0x7e<br>
+<br>
+# CHECK: v_mov_b32_e32 v150, vcc_lo ; encoding: [0x6a,0x02,0x2c,0x7f]<br>
+0x6a 0x02 0x2c 0x7f<br>
+<br>
+# CHECK: v_mov_b32_e32 v199, exec_lo ; encoding: [0x7e,0x02,0x8e,0x7f]<br>
+0x7e 0x02 0x8e 0x7f<br>
+<br>
+# CHECK: v_mov_b32_e32 v222, m0 ; encoding: [0x7c,0x02,0xbc,0x7f]<br>
+0x7c 0x02 0xbc 0x7f<br>
+<br>
+# CHECK: v_mov_b32_e32 v255, -13 ; encoding: [0xcd,0x02,0xfe,0x7f]<br>
+0xcd 0x02 0xfe 0x7f<br>
+<br>
+# CHECK: v_cvt_f32_i32_e32 v153, s98 ; encoding: [0x62,0x0a,0x32,0x7f]<br>
+0x62 0x0a 0x32 0x7f<br>
+<br>
+# CHECK: v_cvt_f32_u32_e32 v33, -4.0 ; encoding: [0xf7,0x0c,0x42,0x7e]<br>
+0xf7 0x0c 0x42 0x7e<br>
\ No newline at end of file<br>
<br>
Added: llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt?rev=261185&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt?rev=261185&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt (added)<br>
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt Wed Feb 17 21:42:32 2016<br>
@@ -0,0 +1,4 @@<br>
+# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s<br>
+<br>
+# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]<br>
+0x00 0x00 0x00 0x7e<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature">~Craig</div>
</div>