[PATCH] Fix a type mismatch assert in SCEV division

[Sanjoy Das]

In http://reviews.llvm.org/D9021#156237, @bcahoon wrote:

> In the test case, the numerator ({0,+,(zext i16 %0 to i32)}<nw><%for.cond7.preheader>) is i32 and the denominator (%0) is i16.  The second divide() call generates a value with type i32 for StepR (the remainder value for the Step).  The types for the values returned by the first divide() call, StartQ and StartR, are both i16.
>
> I think you're suggesting that the check for the type mismatch occur before the calls to divide() in visitAddRecExpr? That seems reasonable.


I was initially suggesting that SCEV should not be attempting to divide integers of different bit-widths, and it should be up to the caller to `sext` or `zext` as needed.  But `visitConstant` clearly tries to do something for differing bit-widths so that assumption was flawed.  Therefore I think this change is okay as it is.

It might be helpful to explicitly document that `SCEVDivision::divide` sign extends the narrower integer to the width of the wider integer before division.  Is it correct to state that invariant here is that if `SCEVDivision::divide` returns `Q` and `R` after dividing `N` by `D` then `sext_if_needed(N)` `==` `sext_if_needed(Q)` `*` `sext_if_needed(D)` `+` `sext_if_needed(R)` where `sext_if_needed` sign extends to the widest of widths of `N` and `R`?  If so, it'll be helpful to document that too.


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