[PATCH] Fix a type mismatch assert in SCEV division

[Brendon Cahoon]

In the test case, the numerator ({0,+,(zext i16 %0 to i32)}<nw><%for.cond7.preheader>) is i32 and the denominator (%0) is i16.  The second divide() call generates a value with type i32 for StepR (the remainder value for the Step).  The types for the values returned by the first divide() call, StartQ and StartR, are both i16.

I think you're suggesting that the check for the type mismatch occur before the calls to divide() in visitAddRecExpr? That seems reasonable.


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  rL LLVM

http://reviews.llvm.org/D9021

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