[PATH][CodeGen] Fix CombineToPostIndexedLoadStore in DAGCombiner.cpp

[Quentin Colombet]

Hi François,

I haven’t looked at the patch yet, but first high level comment.
Please integrate the test case with your patch and use RUN and CHECK lines.

Then, would it be possible to have the new patch uploaded to reviews.llvm.org <http://reviews.llvm.org/> with the full context?

Thanks,
-Quentin
> On Apr 3, 2015, at 6:13 AM, Francois de Ferriere <francois.de-ferriere at st.com> wrote:
> 
> Hi,
> 
>   I post a patch for a missed optimization in the DAGCombiner.cpp LLVM file for the selection of Post Indexed Load and Store operations.
> 
>   The code in the function CombineToPostIndexedLoadStore that checks the uses of an ADD/SUB operation does not correctly check the real uses.
> 
>   Also, in the function canFoldInAddressingMode, VT is computed as the type of the destination/source of a LOAD/STORE operations, instead of the memory type of the operation. On targets which have a scaling factor on the offset of the LOAD/STORE operations, the function may return false for actually valid cases.
> 
>   I could reproduce this problem on the ARM target, a test case that exposes this problem is attached to this mail.
> 
>  Thanks to review it and commit it when it is OK.
> 
>   Regards,
> 
>    - François.
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