[llvm] r229128 - [mips][microMIPS] Delay slot filler: Replace the microMIPS JR with the JRC
Jozef Kolek
jozef.kolek at imgtec.com
Fri Feb 13 09:51:27 PST 2015
Author: jkolek
Date: Fri Feb 13 11:51:27 2015
New Revision: 229128
URL: http://llvm.org/viewvc/llvm-project?rev=229128&view=rev
Log:
[mips][microMIPS] Delay slot filler: Replace the microMIPS JR with the JRC
This patch adds functionality in MIPS delay slot filler such as if delay slot
filler have to put NOP instruction into the delay slot of microMIPS JR
instruction, then instead of emitting NOP this instruction is replaced by
compact jump instruction JRC.
Differential Revision: http://reviews.llvm.org/D7522
Added:
llvm/trunk/test/CodeGen/Mips/micromips-compact-jump.ll
Modified:
llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
llvm/trunk/test/CodeGen/Mips/longbranch.ll
llvm/trunk/test/CodeGen/Mips/micromips-delay-slot-jr.ll
Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=229128&r1=229127&r2=229128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Fri Feb 13 11:51:27 2015
@@ -199,6 +199,9 @@ namespace {
Iter replaceWithCompactBranch(MachineBasicBlock &MBB,
Iter Branch, DebugLoc DL);
+ Iter replaceWithCompactJump(MachineBasicBlock &MBB,
+ Iter Jump, DebugLoc DL);
+
/// This function checks if it is valid to move Candidate to the delay slot
/// and returns true if it isn't. It also updates memory and register
/// dependence information.
@@ -515,6 +518,24 @@ Iter Filler::replaceWithCompactBranch(Ma
return Branch;
}
+// Replace Jumps with the compact jump instruction.
+Iter Filler::replaceWithCompactJump(MachineBasicBlock &MBB,
+ Iter Jump, DebugLoc DL) {
+ const MipsInstrInfo *TII =
+ MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo();
+
+ const MCInstrDesc &NewDesc = TII->get(Mips::JRC16_MM);
+ MachineInstrBuilder MIB = BuildMI(MBB, Jump, DL, NewDesc);
+
+ MIB.addReg(Jump->getOperand(0).getReg());
+
+ Iter tmpIter = Jump;
+ Jump = std::prev(Jump);
+ MBB.erase(tmpIter);
+
+ return Jump;
+}
+
// For given opcode returns opcode of corresponding instruction with short
// delay slot.
static int getEquivalentCallShort(int Opcode) {
@@ -582,17 +603,29 @@ bool Filler::runOnMachineBasicBlock(Mach
// adding NOP replace this instruction with the corresponding compact
// branch instruction, i.e. BEQZC or BNEZC.
unsigned Opcode = I->getOpcode();
- if (InMicroMipsMode &&
- (Opcode == Mips::BEQ || Opcode == Mips::BNE) &&
- ((unsigned) I->getOperand(1).getReg()) == Mips::ZERO) {
-
- I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
-
- } else {
- // Bundle the NOP to the instruction with the delay slot.
- BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
- MIBundleBuilder(MBB, I, std::next(I, 2));
+ if (InMicroMipsMode) {
+ switch (Opcode) {
+ case Mips::BEQ:
+ case Mips::BNE:
+ if (((unsigned) I->getOperand(1).getReg()) == Mips::ZERO) {
+ I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
+ continue;
+ }
+ break;
+ case Mips::JR:
+ case Mips::PseudoReturn:
+ case Mips::PseudoIndirectBranch:
+ // For microMIPS the PseudoReturn and PseudoIndirectBranch are allways
+ // expanded to JR_MM, so they can be replaced with JRC16_MM.
+ I = replaceWithCompactJump(MBB, I, I->getDebugLoc());
+ continue;
+ default:
+ break;
+ }
}
+ // Bundle the NOP to the instruction with the delay slot.
+ BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
+ MIBundleBuilder(MBB, I, std::next(I, 2));
}
return Changed;
Modified: llvm/trunk/test/CodeGen/Mips/longbranch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch.ll?rev=229128&r1=229127&r2=229128&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/longbranch.ll Fri Feb 13 11:51:27 2015
@@ -126,8 +126,7 @@ end:
; MICROMIPS: li16 $[[R2:[0-9]+]], 1
; MICROMIPS: sw16 $[[R2]], 0($[[R1]])
; MICROMIPS: $[[BB2]]:
-; MICROMIPS: jr $ra
-; MICROMIPS: nop
+; MICROMIPS: jrc $ra
; Check the NaCl version. Check that sp change is not in the branch delay slot
Added: llvm/trunk/test/CodeGen/Mips/micromips-compact-jump.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-compact-jump.ll?rev=229128&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-compact-jump.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/micromips-compact-jump.ll Fri Feb 13 11:51:27 2015
@@ -0,0 +1,11 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: -disable-mips-delay-filler -O3 < %s | FileCheck %s
+
+define i32 @foo(i32 signext %a) #0 {
+entry:
+ ret i32 0
+}
+
+declare i32 @bar(i32 signext) #1
+
+; CHECK: jrc
Modified: llvm/trunk/test/CodeGen/Mips/micromips-delay-slot-jr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-delay-slot-jr.ll?rev=229128&r1=229127&r2=229128&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-delay-slot-jr.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/micromips-delay-slot-jr.ll Fri Feb 13 11:51:27 2015
@@ -29,8 +29,7 @@ declare i32 @puts(i8* nocapture readonly
!3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"}
-; CHECK: jr
-; CHECK-NEXT: nop
+; CHECK: jrc
%struct.foostruct = type { [3 x float] }
%struct.barstruct = type { %struct.foostruct, float }
@@ -43,6 +42,5 @@ define float* @spooky(i32 signext %i) #0
}
; CHECK: spooky:
-; CHECK: jr $ra
-; CHECK-NEXT: nop
+; CHECK: jrc $ra
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