[llvm] r226047 - MachineVerifier: Allow undef reads if a matching superreg is defined.
matze at braunis.de
Wed Jan 14 15:04:34 PST 2015
> On Jan 14, 2015, at 2:52 PM, Tom Stellard <tom at stellard.net> wrote:
> On Wed, Jan 14, 2015 at 10:25:15PM -0000, Matthias Braun wrote:
>> Author: matze
>> Date: Wed Jan 14 16:25:14 2015
>> New Revision: 226047
>> URL: http://llvm.org/viewvc/llvm-project?rev=226047&view=rev
>> MachineVerifier: Allow undef reads if a matching superreg is defined.
>> Some pseudo instruction expansions break down a wide register use into
>> multiple uses of smaller sub registers. If the super register was
>> partially undefined the broken down sub registers may be completely
>> undefined now leading to MachineVerifier complaints. Unfortunately
>> liveness information to add the required dead flags is not easily
>> (cheaply) available when expanding pseudo instructions.
> Hi Matthias,
> I ran into a similar problem today, but I don't think this fix will be enough,
> and I was wondering if you had any ideas for how to solve it. Here is a
> simplified example.
> Imagine a target with 4 32-bit registers: s0, s1, s2, s3 which can be
> used individually or as part of 128-bit super register: s[0:3].
> After regalloc, if s0, s1, and s2 are defined individually by 32-bit
> operations and someone asks the register scavenger for a 128-bit
> register. The scavenger will spill the register s[0:3]. Since only 32-bit spills
> are supported, this will be split into 4 spills one for each sub-register:
> spill s0;
> spill s1;
> spill s2;
> spill s3;
> The machine verifier will fail on this, because s3 has never been defined,
> and I think it will still fail even with your patch, because there is no
> implicit use or def of the super-register.
> Any suggestions on how to fix this?
This sounds exactly like the kind of problems I'm working on in the other backends. There are two issues here:
1) Using a super-register when only some of its subregisters are defined -- I simply allowed that in r223896
2) When you start expanding such instructions into a sequence of instructions working on the subregisters later you may get completely undefined subregisters. This is unfortunate but it's just a verifier problem so with the exemption rule in this commit you should add an implicit use of the super register to communicate to the MachineVerifier that you know what you are doing. In your case this would mean adding an implicit use of s[0:3] to all your spill instructions.
I'm not happy with this solution but the alternative of adding infrastructure to express partial defined/undefinedness seemed worse to me...
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