[llvm] r226047 - MachineVerifier: Allow undef reads if a matching superreg is defined.

[Tom Stellard]

On Wed, Jan 14, 2015 at 10:25:15PM -0000, Matthias Braun wrote:
> Author: matze
> Date: Wed Jan 14 16:25:14 2015
> New Revision: 226047
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=226047&view=rev
> Log:
> MachineVerifier: Allow undef reads if a matching superreg is defined.
> 
> Summary:
> Some pseudo instruction expansions break down a wide register use into
> multiple uses of smaller sub registers. If the super register was
> partially undefined the broken down sub registers may be completely
> undefined now leading to MachineVerifier complaints. Unfortunately
> liveness information to add the required dead flags is not easily
> (cheaply) available when expanding pseudo instructions.
> 

Hi Matthias,

I ran into a similar problem today, but I don't think this fix will be enough,
and I was wondering if you had any ideas for how to solve it.  Here is a
simplified example.

Imagine a target with 4 32-bit registers: s0, s1, s2, s3 which can be
used individually or as part of 128-bit super register: s[0:3].

After regalloc, if s0, s1, and s2 are defined individually by 32-bit
operations and someone asks the register scavenger for a 128-bit
register. The scavenger will spill the register s[0:3].  Since only 32-bit spills
are supported, this will be split into 4 spills one for each sub-register:

spill s0;
spill s1;
spill s2;
spill s3;

The machine verifier will fail on this, because s3 has never been defined,
and I think it will still fail even with your patch, because there is no
implicit use or def of the super-register.

Any suggestions on how to fix this?

Thanks,
Tom

> This commit changes the verifier to be quiet if there is an additional
> implicit use of a super register. Pseudo instruction expanders can use
> this to mark cases where partially defined values get potentially broken
> into completely undefined ones.
> 
> Differential Revision: http://reviews.llvm.org/D6973
> 
> Modified:
>     llvm/trunk/lib/CodeGen/MachineVerifier.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=226047&r1=226046&r2=226047&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Wed Jan 14 16:25:14 2015
> @@ -1077,6 +1077,25 @@ void MachineVerifier::checkLiveness(cons
>              }
>            }
>          }
> +        // If there is an additional implicit-use of a super register we stop
> +        // here. By definition we are fine if the super register is not
> +        // (completely) dead, if the complete super register is dead we will
> +        // get a report for its operand.
> +        if (Bad) {
> +          for (const MachineOperand &MOP : MI->uses()) {
> +            if (!MOP.isReg())
> +              continue;
> +            if (!MOP.isImplicit())
> +              continue;
> +            for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
> +                 ++SubRegs) {
> +              if (*SubRegs == Reg) {
> +                Bad = false;
> +                break;
> +              }
> +            }
> +          }
> +        }
>          if (Bad)
>            report("Using an undefined physical register", MO, MONum);
>        } else if (MRI->def_empty(Reg)) {
> 
> 
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