[PATCH] Add intrinsic definitions for unary op AVX instructions [x86]

[Craig Topper]

I believe they used to exist and were removed to reduce the number of
instructions. Instructions aren't completely free. They increase the static
size of the asm writer and intruction info tables. And they have to be
replicated in the folding tables in X86InstrInfo.td (which this patch
neglects to do).

On Tue, Jan 13, 2015 at 12:57 PM, Sanjay Patel <spatel at rotateright.com>
wrote:

> Hi delena, nadav, craig.topper, RKSimon,
>
> This is a 'no functional change' patch to ease writing patterns to fix
> PR21507 ( http://llvm.org/bugs/show_bug.cgi?id=21507 ).
>
> Adding these definitions makes even the existing patterns match other
> instructions, so I assume it was just an oversight that they weren't
> included in the first place.
>
> http://reviews.llvm.org/D6958
>
> Files:
>   lib/Target/X86/X86InstrSSE.td
>
> Index: lib/Target/X86/X86InstrSSE.td
> ===================================================================
> --- lib/Target/X86/X86InstrSSE.td
> +++ lib/Target/X86/X86InstrSSE.td
> @@ -3542,17 +3542,23 @@
>                             OpndItins itins> {
>  let Predicates = [HasAVX], hasSideEffects = 0 in {
>    def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
> -                       (ins FR32:$src1, FR32:$src2),
> -                       !strconcat("v", OpcodeStr,
> -                           "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
> -                []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
> +                      (ins FR32:$src1, FR32:$src2),
> +                      !strconcat("v", OpcodeStr,
> +                                 "ss\t{$src2, $src1, $dst|$dst, $src1,
> $src2}"),
> +                      []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
> +  let isCodeGenOnly = 1 in
> +  def V#NAME#SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
> +                      (ins VR128:$src1, VR128:$src2),
> +                      !strconcat("v", OpcodeStr,
> +                                 "ss\t{$src2, $src1, $dst|$dst, $src1,
> $src2}"),
> +                      []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
>    let mayLoad = 1 in {
>    def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
>                        (ins FR32:$src1,f32mem:$src2),
>                        !strconcat("v", OpcodeStr,
>                                   "ss\t{$src2, $src1, $dst|$dst, $src1,
> $src2}"),
>                        []>, VEX_4V, VEX_LIG,
> -                   Sched<[itins.Sched.Folded, ReadAfterLd]>;
> +                      Sched<[itins.Sched.Folded, ReadAfterLd]>;
>    let isCodeGenOnly = 1 in
>    def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
>                        (ins VR128:$src1, ssmem:$src2),
> @@ -3672,6 +3678,12 @@
>                        !strconcat("v", OpcodeStr,
>                                   "sd\t{$src2, $src1, $dst|$dst, $src1,
> $src2}"),
>                        []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
> +  let isCodeGenOnly = 1 in
> +  def V#NAME#SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
> +                      (ins VR128:$src1, VR128:$src2),
> +                      !strconcat("v", OpcodeStr,
> +                                 "sd\t{$src2, $src1, $dst|$dst, $src1,
> $src2}"),
> +                      []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
>    let mayLoad = 1 in {
>    def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
>                        (ins FR64:$src1,f64mem:$src2),
> @@ -3790,32 +3802,24 @@
>  }
>  let Predicates = [UseAVX] in {
>    def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
> -            (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
> -                                        (COPY_TO_REGCLASS VR128:$src,
> FR32)),
> -                              VR128)>;
> +            (VSQRTSSr_Int (v4f32 (IMPLICIT_DEF)), VR128:$src)>;
>    def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
>              (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
>
>    def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
> -            (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
> -                                        (COPY_TO_REGCLASS VR128:$src,
> FR64)),
> -                              VR128)>;
> +            (VSQRTSDr (v2f64 (IMPLICIT_DEF)), VR128:$src)>;
>    def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
>              (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
>  }
>
>  let Predicates = [HasAVX] in {
>    def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
> -            (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
> -                                         (COPY_TO_REGCLASS VR128:$src,
> FR32)),
> -                              VR128)>;
> +            (VRSQRTSSr_Int (v4f32 (IMPLICIT_DEF)), VR128:$src)>;
>    def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
>              (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
>
>    def : Pat<(int_x86_sse_rcp_ss VR128:$src),
> -            (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
> -                                       (COPY_TO_REGCLASS VR128:$src,
> FR32)),
> -                              VR128)>;
> +            (VRCPSSr_Int (v4f32 (IMPLICIT_DEF)), VR128:$src)>;
>    def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
>              (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
>  }
>
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>



-- 
~Craig
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