<div dir="ltr">I believe they used to exist and were removed to reduce the number of instructions. Instructions aren't completely free. They increase the static size of the asm writer and intruction info tables. And they have to be replicated in the folding tables in X86InstrInfo.td (which this patch neglects to do).</div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jan 13, 2015 at 12:57 PM, Sanjay Patel <span dir="ltr"><<a href="mailto:spatel@rotateright.com" target="_blank">spatel@rotateright.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi delena, nadav, craig.topper, RKSimon,<br>
<br>
This is a 'no functional change' patch to ease writing patterns to fix PR21507 ( <a href="http://llvm.org/bugs/show_bug.cgi?id=21507" target="_blank">http://llvm.org/bugs/show_bug.cgi?id=21507</a> ).<br>
<br>
Adding these definitions makes even the existing patterns match other instructions, so I assume it was just an oversight that they weren't included in the first place.<br>
<br>
<a href="http://reviews.llvm.org/D6958" target="_blank">http://reviews.llvm.org/D6958</a><br>
<br>
Files:<br>
  lib/Target/X86/X86InstrSSE.td<br>
<br>
Index: lib/Target/X86/X86InstrSSE.td<br>
===================================================================<br>
--- lib/Target/X86/X86InstrSSE.td<br>
+++ lib/Target/X86/X86InstrSSE.td<br>
@@ -3542,17 +3542,23 @@<br>
                            OpndItins itins> {<br>
 let Predicates = [HasAVX], hasSideEffects = 0 in {<br>
   def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),<br>
-                       (ins FR32:$src1, FR32:$src2),<br>
-                       !strconcat("v", OpcodeStr,<br>
-                           "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
-                []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;<br>
+                      (ins FR32:$src1, FR32:$src2),<br>
+                      !strconcat("v", OpcodeStr,<br>
+                                 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
+                      []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;<br>
+  let isCodeGenOnly = 1 in<br>
+  def V#NAME#SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),<br>
+                      (ins VR128:$src1, VR128:$src2),<br>
+                      !strconcat("v", OpcodeStr,<br>
+                                 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
+                      []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;<br>
   let mayLoad = 1 in {<br>
   def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),<br>
                       (ins FR32:$src1,f32mem:$src2),<br>
                       !strconcat("v", OpcodeStr,<br>
                                  "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
                       []>, VEX_4V, VEX_LIG,<br>
-                   Sched<[itins.Sched.Folded, ReadAfterLd]>;<br>
+                      Sched<[itins.Sched.Folded, ReadAfterLd]>;<br>
   let isCodeGenOnly = 1 in<br>
   def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),<br>
                       (ins VR128:$src1, ssmem:$src2),<br>
@@ -3672,6 +3678,12 @@<br>
                       !strconcat("v", OpcodeStr,<br>
                                  "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
                       []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;<br>
+  let isCodeGenOnly = 1 in<br>
+  def V#NAME#SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),<br>
+                      (ins VR128:$src1, VR128:$src2),<br>
+                      !strconcat("v", OpcodeStr,<br>
+                                 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
+                      []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;<br>
   let mayLoad = 1 in {<br>
   def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),<br>
                       (ins FR64:$src1,f64mem:$src2),<br>
@@ -3790,32 +3802,24 @@<br>
 }<br>
 let Predicates = [UseAVX] in {<br>
   def : Pat<(int_x86_sse_sqrt_ss VR128:$src),<br>
-            (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),<br>
-                                        (COPY_TO_REGCLASS VR128:$src, FR32)),<br>
-                              VR128)>;<br>
+            (VSQRTSSr_Int (v4f32 (IMPLICIT_DEF)), VR128:$src)>;<br>
   def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),<br>
             (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;<br>
<br>
   def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),<br>
-            (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),<br>
-                                        (COPY_TO_REGCLASS VR128:$src, FR64)),<br>
-                              VR128)>;<br>
+            (VSQRTSDr (v2f64 (IMPLICIT_DEF)), VR128:$src)>;<br>
   def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),<br>
             (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;<br>
 }<br>
<br>
 let Predicates = [HasAVX] in {<br>
   def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),<br>
-            (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),<br>
-                                         (COPY_TO_REGCLASS VR128:$src, FR32)),<br>
-                              VR128)>;<br>
+            (VRSQRTSSr_Int (v4f32 (IMPLICIT_DEF)), VR128:$src)>;<br>
   def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),<br>
             (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;<br>
<br>
   def : Pat<(int_x86_sse_rcp_ss VR128:$src),<br>
-            (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),<br>
-                                       (COPY_TO_REGCLASS VR128:$src, FR32)),<br>
-                              VR128)>;<br>
+            (VRCPSSr_Int (v4f32 (IMPLICIT_DEF)), VR128:$src)>;<br>
   def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),<br>
             (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;<br>
 }<br>
<br>
EMAIL PREFERENCES<br>
  <a href="http://reviews.llvm.org/settings/panel/emailpreferences/" target="_blank">http://reviews.llvm.org/settings/panel/emailpreferences/</a><br>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature">~Craig</div>
</div>