[PATCH] Fix bug in GPR to FPR moves in PPC64LE

Samuel F Antao sfantao at us.ibm.com
Fri Oct 10 09:02:01 PDT 2014


Hi Bill,

No problem! Thanks for letting me know!

Samuel



From:	Bill Schmidt <wschmidt at linux.vnet.ibm.com>
To:	Samuel F Antao/Watson/IBM at IBMUS
Cc:	llvm-commits at cs.uiuc.edu, seuer at linux.vnet.ibm.com
Date:	10/10/2014 11:22 AM
Subject:	Re: [PATCH] Fix bug in GPR to FPR moves in PPC64LE



Hi Samuel,

I went ahead and added the new feature in revisions 219501 (llvm) and
219502 (clang).  I found myself needing it as well, so decided to just
get it done.  Hope this didn't step on any toes.  Anyway, you can now
test for legal use of the move instructions with hasPower8Vector() in
the subtarget class.

Thanks,
Bill

On Thu, 2014-10-09 at 17:05 -0400, Samuel F Antao wrote:
> Hal, Bill,
>
>
> Thanks for the review and suggestions! Committed in r219441.
>
>
> I'll create a new patch with the new move instructions. Creating the
> new feature sounds like a good idea!
>
>
> Thanks again,
> Samuel
>
> 2014-10-09 14:57 GMT-04:00 Bill Schmidt <wschmidt at linux.vnet.ibm.com>:
>         On Thu, 2014-10-09 at 14:16 -0400, Samuel F Antao wrote:
>         > Hi all,
>         >
>         >
>         > The current implementation of GPR->FPR register moves uses a
>         stack
>         > slot. This mechanism writes a double word and reads a word.
>         In
>         > big-endian the load address must be displaced by 4-bytes in
>         order to
>         > get the right value. In little endian this is no longer
>         required. This
>         > patch fixes the issue and adds LE regression tests to
>         > fast-isel-conversion which currently expose this problem.
>         >
>         Thanks, Samuel!  LGTM.
>
>         > This move can be done using the VSX capabilities that are
>         currently
>         > deactivated due to some other problems. I understand Bill
>         and Bill are
>         > fixing some of the VSX issues in FastISel, but this patch
>         seems to be
>         > orthogonal to that. I can contribute another implementation
>         of the
>         > moves using these instructions, which I've already
>         implemented, once
>         > it is okay to activate VSX for little endian.
>         >
>         Well, we will need to add a feature for ISA 2.07 (thanks for
>         that fix,
>         btw) vector support before the direct move instructions can be
>         used.
>         Currently FeatureVSX implies only ISA 2.06 support, which is
>         all that's
>         been (partially) implemented at this point.  Probably
>         something like
>         FeatureP8Vector to denote the changes to both VMX and VSX
>         instructions
>         for 2.07.
>
>         Bill
>         >
>         > Thanks!
>         > Samuel
>
>
>         _______________________________________________
>         llvm-commits mailing list
>         llvm-commits at cs.uiuc.edu
>         http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
>


-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20141010/51272bb5/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: graycol.gif
Type: image/gif
Size: 105 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20141010/51272bb5/attachment.gif>


More information about the llvm-commits mailing list