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<p><font size="2" face="sans-serif">Hi Bill,</font><br>
<br>
<font size="2" face="sans-serif">No problem! Thanks for letting me know!</font><br>
<br>
<font size="2" face="sans-serif">Samuel</font><br>
<br>
<img width="16" height="16" src="cid:1__=0ABBF7FEDFC47D018f9e8a93df938@us.ibm.com" border="0" alt="Inactive hide details for Bill Schmidt ---10/10/2014 11:22:10 AM---Hi Samuel, I went ahead and added the new feature in revisio"><font size="2" color="#424282" face="sans-serif">Bill Schmidt ---10/10/2014 11:22:10 AM---Hi Samuel, I went ahead and added the new feature in revisions 219501 (llvm) and</font><br>
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<font size="1" color="#5F5F5F" face="sans-serif">From: </font><font size="1" face="sans-serif">Bill Schmidt <wschmidt@linux.vnet.ibm.com></font><br>
<font size="1" color="#5F5F5F" face="sans-serif">To: </font><font size="1" face="sans-serif">Samuel F Antao/Watson/IBM@IBMUS</font><br>
<font size="1" color="#5F5F5F" face="sans-serif">Cc: </font><font size="1" face="sans-serif">llvm-commits@cs.uiuc.edu, seuer@linux.vnet.ibm.com</font><br>
<font size="1" color="#5F5F5F" face="sans-serif">Date: </font><font size="1" face="sans-serif">10/10/2014 11:22 AM</font><br>
<font size="1" color="#5F5F5F" face="sans-serif">Subject: </font><font size="1" face="sans-serif">Re: [PATCH] Fix bug in GPR to FPR moves in PPC64LE</font><br>
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<tt><font size="2">Hi Samuel,<br>
<br>
I went ahead and added the new feature in revisions 219501 (llvm) and<br>
219502 (clang). I found myself needing it as well, so decided to just<br>
get it done. Hope this didn't step on any toes. Anyway, you can now<br>
test for legal use of the move instructions with hasPower8Vector() in<br>
the subtarget class.<br>
<br>
Thanks,<br>
Bill<br>
<br>
On Thu, 2014-10-09 at 17:05 -0400, Samuel F Antao wrote:<br>
> Hal, Bill,<br>
> <br>
> <br>
> Thanks for the review and suggestions! Committed in r219441.<br>
> <br>
> <br>
> I'll create a new patch with the new move instructions. Creating the<br>
> new feature sounds like a good idea!<br>
> <br>
> <br>
> Thanks again,<br>
> Samuel<br>
> <br>
> 2014-10-09 14:57 GMT-04:00 Bill Schmidt <wschmidt@linux.vnet.ibm.com>:<br>
> On Thu, 2014-10-09 at 14:16 -0400, Samuel F Antao wrote:<br>
> > Hi all,<br>
> ><br>
> ><br>
> > The current implementation of GPR->FPR register moves uses a<br>
> stack<br>
> > slot. This mechanism writes a double word and reads a word.<br>
> In<br>
> > big-endian the load address must be displaced by 4-bytes in<br>
> order to<br>
> > get the right value. In little endian this is no longer<br>
> required. This<br>
> > patch fixes the issue and adds LE regression tests to<br>
> > fast-isel-conversion which currently expose this problem.<br>
> ><br>
> Thanks, Samuel! LGTM.<br>
> <br>
> > This move can be done using the VSX capabilities that are<br>
> currently<br>
> > deactivated due to some other problems. I understand Bill<br>
> and Bill are<br>
> > fixing some of the VSX issues in FastISel, but this patch<br>
> seems to be<br>
> > orthogonal to that. I can contribute another implementation<br>
> of the<br>
> > moves using these instructions, which I've already<br>
> implemented, once<br>
> > it is okay to activate VSX for little endian.<br>
> ><br>
> Well, we will need to add a feature for ISA 2.07 (thanks for<br>
> that fix,<br>
> btw) vector support before the direct move instructions can be<br>
> used.<br>
> Currently FeatureVSX implies only ISA 2.06 support, which is<br>
> all that's<br>
> been (partially) implemented at this point. Probably<br>
> something like<br>
> FeatureP8Vector to denote the changes to both VMX and VSX<br>
> instructions<br>
> for 2.07.<br>
> <br>
> Bill<br>
> ><br>
> > Thanks!<br>
> > Samuel<br>
> <br>
> <br>
> _______________________________________________<br>
> llvm-commits mailing list<br>
> llvm-commits@cs.uiuc.edu<br>
> </font></tt><tt><font size="2"><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></font></tt><tt><font size="2"><br>
> <br>
> <br>
> <br>
<br>
<br>
</font></tt><br>
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