[PATCH] [llvm] [Hexagon] Adding tests, TableGen entries, and code for emitting add opcode.

[Sid Manning]

================
Comment at: unittests/MC/Hexagon/HexagonMCCodeEmitterTest.cpp:57
@@ +56,3 @@
+/// \brief Instruction encoding with different register numbers
+TEST(HexagonMCCodeEmitter, add_Rd_Rs_Rt) {
+  std::string str;
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colinl wrote:
> rafael wrote:
> > Why can't you test this with llvm-mc?  It seems a much better way of testing this then by manually creating instructions in a unit test.
> > 
> The plan was to get the integrated assember updated before putting in the assembler parser which is non-existent at the moment.
> 
> We thought it could also help narrowing down issues by testing the code emission in isolation.
> 
> What do you think?
That is right.  The hexagon assembly language syntax is somewhat C-like and violates some of the assumptions the MC assembler makes.

We want to get the TD files updated with encoding bits and update the rest of MCTargetDesc so that object files can be directly emitted.  Using this test framework allows us to add the encoding bits and have a directed test for each instruction.

http://reviews.llvm.org/D5624