[PATCH] [Power] Use lwsync for non-seq_cst fences

hfinkel at anl.gov hfinkel at anl.gov
Thu Oct 2 21:14:42 PDT 2014


Please add a test run with ppc440 to make sure we still get msync.

Comment at: lib/Target/PowerPC/PPCInstrInfo.td:2559
@@ -2553,1 +2558,3 @@
+def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
+def : Pat<(atomic_fence (imm),   (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
By the way, what happens to AtomicOrdering == 2 (which is Monotonic). Is that (should that be) a noop?


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