[llvm] r218050 - Fixing a bunch of -Woverloaded-virtual warnings due to hiding getSubtargetImpl from the base class. NFC.
David Blaikie
dblaikie at gmail.com
Thu Sep 18 08:55:49 PDT 2014
On Thu, Sep 18, 2014 at 6:27 AM, Aaron Ballman <aaron at aaronballman.com>
wrote:
> Author: aaronballman
> Date: Thu Sep 18 08:27:14 2014
> New Revision: 218050
>
> URL: http://llvm.org/viewvc/llvm-project?rev=218050&view=rev
> Log:
> Fixing a bunch of -Woverloaded-virtual warnings due to hiding
> getSubtargetImpl from the base class. NFC.
>
Which compiler is producing that warning here?
I /think/ this is one of those cases where we improved the Clang warning
and should just disable the GCC one.
(there's some debate about what the /point/ of this warning is, which is
fair - but I tuned Clang's to detect the cases where someone tried to
override and accidentally overloaded - which isn't the case here. The base
class has a couple of virtual methods, the derived class correctly overrode
one of them. I don't think this is a major source of bugs/worth fixing,
possibly)
(the gap of course is that you can still end up with this problem:
struct base { virtual void func(int); virtual void func(bool); };
struct derived : base { void func(bool) override; void stuff() { func(42);
/* oops, this calls func(bool) because shadowing */ } };
hence the debate about what the purpose of the warning is)
>
> Modified:
> llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.h
> llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h
> llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h
> llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
> llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h
> llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
> llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h
> llvm/trunk/lib/Target/X86/X86TargetMachine.h
> llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h Thu Sep 18
> 08:27:14 2014
> @@ -31,6 +31,7 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL, bool IsLittleEndian);
>
> + using LLVMTargetMachine::getSubtargetImpl;
> const AArch64Subtarget *getSubtargetImpl() const override {
> return &Subtarget;
> }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Thu Sep 18 08:27:14 2014
> @@ -32,6 +32,7 @@ public:
> CodeGenOpt::Level OL,
> bool isLittle);
>
> + using LLVMTargetMachine::getSubtargetImpl;
> const ARMSubtarget *getSubtargetImpl() const override { return
> &Subtarget; }
>
> /// \brief Register ARM analysis passes with a pass manager.
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.h Thu Sep 18
> 08:27:14 2014
> @@ -31,6 +31,7 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL);
>
> + using LLVMTargetMachine::getSubtargetImpl;
> const HexagonSubtarget *getSubtargetImpl() const override {
> return &Subtarget;
> }
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h Thu Sep 18 08:27:14
> 2014
> @@ -32,6 +32,7 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL);
>
> + using LLVMTargetMachine::getSubtargetImpl;
> const MSP430Subtarget *getSubtargetImpl() const override {
> return &Subtarget;
> }
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Thu Sep 18 08:27:14 2014
> @@ -39,6 +39,7 @@ public:
>
> void addAnalysisPasses(PassManagerBase &PM) override;
>
> + using LLVMTargetMachine::getSubtargetImpl;
> const MipsSubtarget *getSubtargetImpl() const override {
> if (Subtarget)
> return Subtarget;
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h Thu Sep 18 08:27:14
> 2014
> @@ -35,6 +35,7 @@ public:
> const TargetOptions &Options, Reloc::Model RM,
> CodeModel::Model CM, CodeGenOpt::Level OP, bool
> is64bit);
>
> + using LLVMTargetMachine::getSubtargetImpl;
> const NVPTXSubtarget *getSubtargetImpl() const override { return
> &Subtarget; }
>
> ManagedStringPool *getManagedStrPool() const {
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Thu Sep 18 08:27:14
> 2014
> @@ -32,6 +32,7 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL);
>
> + using LLVMTargetMachine::getSubtargetImpl;
> const PPCSubtarget *getSubtargetImpl() const override { return
> &Subtarget; }
>
> // Pass Pipeline Configuration
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h Thu Sep 18 08:27:14
> 2014
> @@ -33,6 +33,8 @@ public:
> StringRef CPU, TargetOptions Options, Reloc::Model
> RM,
> CodeModel::Model CM, CodeGenOpt::Level OL);
> ~AMDGPUTargetMachine();
> +
> + using LLVMTargetMachine::getSubtargetImpl;
> const AMDGPUSubtarget *getSubtargetImpl() const override {
> return &Subtarget;
> }
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Thu Sep 18 08:27:14
> 2014
> @@ -28,6 +28,7 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL, bool is64bit);
>
> + using LLVMTargetMachine::getSubtargetImpl;
> const SparcSubtarget *getSubtargetImpl() const override { return
> &Subtarget; }
>
> // Pass Pipeline Configuration
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h Thu Sep 18
> 08:27:14 2014
> @@ -32,6 +32,7 @@ public:
> CodeGenOpt::Level OL);
>
> // Override TargetMachine.
> + using LLVMTargetMachine::getSubtargetImpl;
> const SystemZSubtarget *getSubtargetImpl() const override {
> return &Subtarget;
> }
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Thu Sep 18 08:27:14 2014
> @@ -31,6 +31,8 @@ public:
> StringRef CPU, StringRef FS, const TargetOptions
> &Options,
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL);
> +
> + using LLVMTargetMachine::getSubtargetImpl;
> const X86Subtarget *getSubtargetImpl() const override { return
> &Subtarget; }
>
> /// \brief Register X86 analysis passes with a pass manager.
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=218050&r1=218049&r2=218050&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Thu Sep 18 08:27:14
> 2014
> @@ -27,6 +27,7 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL);
>
> + using LLVMTargetMachine::getSubtargetImpl;
> const XCoreSubtarget *getSubtargetImpl() const override { return
> &Subtarget; }
>
> // Pass Pipeline Configuration
>
>
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