[PATCH] ARM: Enable DP copy, load and store instructions for FPv4-SP

[Oliver Stannard]

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Comment at: test/CodeGen/ARM/aapcs-hfa-code.ll:79
@@ -80,2 +78,3 @@
 ; CHECK-M4F: movs [[ONEHI:r[0-9]+]], #0
+; CHECK-M4F: movs [[ONELO:r[0-9]+]], #0
 ; CHECK-M4F: movt [[ONEHI]], #16368
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Renato Golin wrote:
> A bit fragile this change, no? Shouldn't this also be a DAG check?
I'm not sure how this can be done. If I was to make the movs lines DAG checks, they could match in either order, but ONEHI and ONELO would be swapped, so the movt and strd lines would fail to match. Making any more checks DAGs would cause this test to match even if the registers were in the wrong order (swapping ONEHI and ONELO in the strd is a plausible failure mode).

http://reviews.llvm.org/D4907