[PATCH] ARMEB: Vector extend operations
james.molloy at arm.com
Thu Jun 12 06:28:46 PDT 2014
No, I don't think so. As I mentioned in my previous review comment, I would like to see more explanations in the code and commit message before I'm happy.
Also, I believe you're actually editing the code that generates this VLDR/VREV pair now. So I think that for 64-bit to 128-bit vector extloads, you can just use the little-endian version, not predicate it, and make little-endian generate an LD1 instead of a LDR.
Also, I take it this affects AArch64 too?
> -----Original Message-----
> From: Konrad Anheim [mailto:kanheim at a-bix.com]
> Sent: 12 June 2014 14:27
> To: reviews+D4043+public+b5dcb86c5807ced6 at reviews.llvm.org
> Cc: cpirker at a-bix.com; James Molloy; Amara Emerson; llvm-
> commits at cs.uiuc.edu
> Subject: Re: [PATCH] ARMEB: Vector extend operations
> Hi James,
> Would you please accept http://reviews.llvm.org/D4043 as functional OK,
> and would consider any VREV, VLD optimization as separate issue?
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