[PATCH] ARM: Implement big endian bit-conversion for NEON types

[James Molloy]

Hi Christian,

> The patch converts vector arguments into integer format (and vice versa) when passing vectors as function arguments, as required by the ABI.

Whereabouts, exactly? I see no changes to the calling convention .td or the calling convention parts of ISel lowering.

Cheers,

James

================
Comment at: lib/Target/ARM/ARMFastISel.cpp:192
@@ -191,1 +191,3 @@
 
+    const TargetLowering* getTargetLowering() { return TM.getTargetLowering(); }
+
----------------
Christian Pirker wrote:
> James Molloy wrote:
> > This function seems unused?
> This function is required to evaluate the [IsBE] predicate for the bitconversion rules that specify the VREV instructions.
But that predicate isn't defined anywhere in this patch.

================
Comment at: lib/Target/ARM/ARMInstrNEON.td:2369
@@ -2368,3 +2368,3 @@
 def : Pat<(v2f64 (word_alignedload addrmode6:$addr)),
-          (VLD1q32 addrmode6:$addr)>;
+          (VLD1q32 addrmode6:$addr)>, Requires<[IsLE]>;
 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
----------------
Christian Pirker wrote:
> James Molloy wrote:
> > Why are these not allowed in big-endian mode? and why only these patterns?
> v2f64 is not compatible with v4i32 in big endian mode (a vrev instruction would be needed). All other patterns like v8i8,... are already disabled in big endian mode. Not sure why this specific rule was left active for both endian modes.
Ah yes, I see. Thanks.

http://reviews.llvm.org/D3651