[PATCH] Add custom lowering for add/sub with overflow ARM
lgg at apple.com
Tue May 6 13:46:38 PDT 2014
On May 2, 2014, at 11:40 PM, Tim Northover <t.p.northover at gmail.com> wrote:
> Hi Louis,
> On 3 May 2014 01:43, Louis Gerbarg <lgg at apple.com> wrote:
>> The attached patch provides custom lowering of overflow intrinsics for the ARM architecture.
> As Pete said, a very good idea!
> I think I'd prefer it if the tests also tracked data dependencies as
> well as just the instructions used though. If you swapped some
> operands around the results might be disastrous.
>> add r2, r0, r1
>> mov r1, #1
>> cmp r2, r0
>> movvc r1, #0
> Couldn't this be simplified to:
> adds r2, r0, r1
> mov r1, #1
> movvc r1, #0
> ? This would probably involve adding ARMISD::ADDS and ARMISD::SUBS
> nodes (see ARM64 for reference, it already has them).
Yes, this can be simplified further. I took another look at this morning. The issue that prevented me from doing it in the first place is that the arm backend handles the CPSR somewhat differently than ARM64. There are already somewhat analogous nodes (ARMISD::ADDC and ARMISD::SUBC), but they decide whether or not to set flags based on the liveness of the CPSR, so I need to figure out how to get that wired up. I don’t think adding explicit ADDS/SUBS nodes would make that any simpler because I suspect they would have to deal with equivalent CPSR issues in the tablegen files.
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