[PATCH] [InstCombine] Combine adjacent i8 loads.

[Raul Silvera]

I agree this combining can in theory be done as part of SLP vectorization,
targeting wider scalar registers as a limited form of vector hardware,
supporting wider loads/stores and some bitwise operations. That would
likely catch more cases than what can be done with a small standalone pass.



Raúl E Silvera | SWE | rsilvera at google.com | *408-789-2846*



On Thu, May 1, 2014 at 3:52 PM, Chandler Carruth <chandlerc at gmail.com>wrote:

> I think I would prefer to implement this as a standalone pass until we have
> some clear phase ordering need for it in a utility like instcombine.
>
> My suggestion: a pass that runs right after GVN.
>
> I would also use the domtree rather than the basic block structure.
>
> I think it really needs to handle arbitrary sizes, and both loads and
> stores. You don't want to scan multiple times for this.
>
> But after thinking all of this, it strikes me that the work done here is
> *very* similar to the work done by the SLP vectorizer for loads and stores.
> I think there is at least the possibility that this should be done by the
> SLP vectorizer, or that some of the logic should be shared. I'd appreciate
> Arnold's, Raul's, Nadav's, and Hal's thoughts on this idea.
>
> http://reviews.llvm.org/D3580
>
>
>
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