[PATCH] [InstCombine] Combine adjacent i8 loads.

[Raul Silvera]

I agree this combining can in theory be done as part of SLP vectorization,
targeting wider scalar registers as a limited form of vector hardware,
supporting wider loads/stores and some bitwise operations. That would
likely catch more cases than what can be done with a small standalone pass.



Raúl E Silvera | SWE | rsilvera at google.com | *408-789-2846*

http://reviews.llvm.org/D3580