[PATCH] Teach the DAGCombiner how to fold a OR of two shufflevector into a single shufflevector node

Hal Finkel hfinkel at anl.gov
Wed Mar 5 09:55:13 PST 2014

----- Original Message -----
> From: "Nadav Rotem" <nrotem at apple.com>
> To: "Andrea Di Biagio" <andrea.dibiagio at gmail.com>
> Cc: "llvm-commits at cs.uiuc.edu for LLVM" <llvm-commits at cs.uiuc.edu>
> Sent: Wednesday, March 5, 2014 11:47:53 AM
> Subject: Re: [PATCH] Teach the DAGCombiner how to fold a OR of two	shufflevector into a single shufflevector node
> Hi Andrea,
> Thanks for working on this.  Lowering shuffles is really difficult
> and we have >1000 LOC in the x86 backends for lowering shuffles.  It
> is really difficult to predict which shuffles are supported and
> which patterns result in slow code. Until now LLVM was *not* to
> introducing new shuffle patterns. The idea was that the users that
> generate the shuffle patterns should know if the patterns are
> supported by the target. This makes sense for users that write their
> own math libraries using the clang vector syntax. Your patch
> introduces new shuffle patterns that some backends may not know how
> to lower. I think that the code should be okay for AVX and AVX2
> because you are not introducing cross-lane shuffles. So, I suggest
> that you move this patch into the X86 backend and protect it with
> the hasAVX flags. Does that make sense?

Is this not what TLI->isShuffleMaskLegal is for? We avoid introducing new shuffle patterns at the IR level, especially during canonicalization, because we don't want to use target information at that stage. In the SDAG, I think that the situation is different. There we should use TLI->isShuffleMaskLegal (at the other associated legality checks) to control these kinds of optimizations. Opinions?


> Thanks,
> Nadav
> On Feb 26, 2014, at 7:07 AM, Andrea Di Biagio
> <andrea.dibiagio at gmail.com> wrote:
> > <patch-dagcombine.diff>
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Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory

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