[llvm] r192957 - CodeGen: Emit a libcall if the target doesn't support 16-byte wide atomics
David Majnemer
david.majnemer at gmail.com
Fri Oct 18 07:56:15 PDT 2013
Unintentional, 'arc commit' != 'svn commit'
Remedied in r192978.
Thanks!
--
David Majnemer
On Fri, Oct 18, 2013 at 7:43 AM, Rafael Espíndola <
rafael.espindola at gmail.com> wrote:
> testcase?
>
> On 18 October 2013 04:03, David Majnemer <david.majnemer at gmail.com> wrote:
> > Author: majnemer
> > Date: Fri Oct 18 03:03:43 2013
> > New Revision: 192957
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=192957&view=rev
> > Log:
> > CodeGen: Emit a libcall if the target doesn't support 16-byte wide
> atomics
> >
> > There are targets that support i128 sized scalars but cannot emit
> > instructions that modify them directly. The proper thing to do is to
> > emit a libcall.
> >
> > This fixes PR17481.
> >
> > Modified:
> > llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h
> > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> > llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
> >
> > Modified: llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h?rev=192957&r1=192956&r2=192957&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h (original)
> > +++ llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h Fri Oct 18
> 03:03:43 2013
> > @@ -325,34 +325,42 @@ namespace RTLIB {
> > SYNC_VAL_COMPARE_AND_SWAP_2,
> > SYNC_VAL_COMPARE_AND_SWAP_4,
> > SYNC_VAL_COMPARE_AND_SWAP_8,
> > + SYNC_VAL_COMPARE_AND_SWAP_16,
> > SYNC_LOCK_TEST_AND_SET_1,
> > SYNC_LOCK_TEST_AND_SET_2,
> > SYNC_LOCK_TEST_AND_SET_4,
> > SYNC_LOCK_TEST_AND_SET_8,
> > + SYNC_LOCK_TEST_AND_SET_16,
> > SYNC_FETCH_AND_ADD_1,
> > SYNC_FETCH_AND_ADD_2,
> > SYNC_FETCH_AND_ADD_4,
> > SYNC_FETCH_AND_ADD_8,
> > + SYNC_FETCH_AND_ADD_16,
> > SYNC_FETCH_AND_SUB_1,
> > SYNC_FETCH_AND_SUB_2,
> > SYNC_FETCH_AND_SUB_4,
> > SYNC_FETCH_AND_SUB_8,
> > + SYNC_FETCH_AND_SUB_16,
> > SYNC_FETCH_AND_AND_1,
> > SYNC_FETCH_AND_AND_2,
> > SYNC_FETCH_AND_AND_4,
> > SYNC_FETCH_AND_AND_8,
> > + SYNC_FETCH_AND_AND_16,
> > SYNC_FETCH_AND_OR_1,
> > SYNC_FETCH_AND_OR_2,
> > SYNC_FETCH_AND_OR_4,
> > SYNC_FETCH_AND_OR_8,
> > + SYNC_FETCH_AND_OR_16,
> > SYNC_FETCH_AND_XOR_1,
> > SYNC_FETCH_AND_XOR_2,
> > SYNC_FETCH_AND_XOR_4,
> > SYNC_FETCH_AND_XOR_8,
> > + SYNC_FETCH_AND_XOR_16,
> > SYNC_FETCH_AND_NAND_1,
> > SYNC_FETCH_AND_NAND_2,
> > SYNC_FETCH_AND_NAND_4,
> > SYNC_FETCH_AND_NAND_8,
> > + SYNC_FETCH_AND_NAND_16,
> >
> > // Stack Protector Fail.
> > STACKPROTECTOR_CHECK_FAIL,
> >
> > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=192957&r1=192956&r2=192957&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 18
> 03:03:43 2013
> > @@ -2661,6 +2661,7 @@ std::pair <SDValue, SDValue> SelectionDA
> > case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
> > }
> > break;
> > case ISD::ATOMIC_CMP_SWAP:
> > @@ -2670,6 +2671,7 @@ std::pair <SDValue, SDValue> SelectionDA
> > case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_ADD:
> > @@ -2679,6 +2681,7 @@ std::pair <SDValue, SDValue> SelectionDA
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_SUB:
> > @@ -2688,6 +2691,7 @@ std::pair <SDValue, SDValue> SelectionDA
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_AND:
> > @@ -2697,6 +2701,7 @@ std::pair <SDValue, SDValue> SelectionDA
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_OR:
> > @@ -2706,6 +2711,7 @@ std::pair <SDValue, SDValue> SelectionDA
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_XOR:
> > @@ -2715,6 +2721,7 @@ std::pair <SDValue, SDValue> SelectionDA
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_NAND:
> > @@ -2724,6 +2731,7 @@ std::pair <SDValue, SDValue> SelectionDA
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
> > }
> > break;
> > }
> >
> > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=192957&r1=192956&r2=192957&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> (original)
> > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Fri Oct
> 18 03:03:43 2013
> > @@ -1194,6 +1194,7 @@ std::pair <SDValue, SDValue> DAGTypeLega
> > case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
> > }
> > break;
> > case ISD::ATOMIC_CMP_SWAP:
> > @@ -1203,6 +1204,7 @@ std::pair <SDValue, SDValue> DAGTypeLega
> > case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_ADD:
> > @@ -1212,6 +1214,7 @@ std::pair <SDValue, SDValue> DAGTypeLega
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_SUB:
> > @@ -1221,6 +1224,7 @@ std::pair <SDValue, SDValue> DAGTypeLega
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_AND:
> > @@ -1230,6 +1234,7 @@ std::pair <SDValue, SDValue> DAGTypeLega
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_OR:
> > @@ -1239,6 +1244,7 @@ std::pair <SDValue, SDValue> DAGTypeLega
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_XOR:
> > @@ -1248,6 +1254,7 @@ std::pair <SDValue, SDValue> DAGTypeLega
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
> > }
> > break;
> > case ISD::ATOMIC_LOAD_NAND:
> > @@ -1257,6 +1264,7 @@ std::pair <SDValue, SDValue> DAGTypeLega
> > case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
> > case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
> > case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
> > + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
> > }
> > break;
> > }
> >
> > Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=192957&r1=192956&r2=192957&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)
> > +++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Fri Oct 18 03:03:43
> 2013
> > @@ -318,34 +318,42 @@ static void InitLibcallNames(const char
> > Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] =
> "__sync_val_compare_and_swap_2";
> > Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] =
> "__sync_val_compare_and_swap_4";
> > Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] =
> "__sync_val_compare_and_swap_8";
> > + Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] =
> "__sync_val_compare_and_swap_16";
> > Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
> > Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
> > Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
> > Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
> > + Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] =
> "__sync_lock_test_and_set_16";
> > Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
> > Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
> > Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
> > Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
> > + Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
> > Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
> > Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
> > Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
> > Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
> > + Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
> > Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
> > Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
> > Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
> > Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
> > + Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
> > Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
> > Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
> > Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
> > Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
> > + Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
> > Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
> > Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
> > Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
> > Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
> > + Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
> > Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
> > Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
> > Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
> > Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
> > + Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
> >
> > if (Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU) {
> > Names[RTLIB::SINCOS_F32] = "sincosf";
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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