<div dir="ltr">Unintentional, 'arc commit' != 'svn commit'<div><br></div><div>Remedied in r192978.</div><div><br></div><div>Thanks!</div><div>-- </div><div>David Majnemer</div><div><br></div></div><div class="gmail_extra">
<br><br><div class="gmail_quote">On Fri, Oct 18, 2013 at 7:43 AM, Rafael Espíndola <span dir="ltr"><<a href="mailto:rafael.espindola@gmail.com" target="_blank">rafael.espindola@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
testcase?<br>
<div class="HOEnZb"><div class="h5"><br>
On 18 October 2013 04:03, David Majnemer <<a href="mailto:david.majnemer@gmail.com">david.majnemer@gmail.com</a>> wrote:<br>
> Author: majnemer<br>
> Date: Fri Oct 18 03:03:43 2013<br>
> New Revision: 192957<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=192957&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=192957&view=rev</a><br>
> Log:<br>
> CodeGen: Emit a libcall if the target doesn't support 16-byte wide atomics<br>
><br>
> There are targets that support i128 sized scalars but cannot emit<br>
> instructions that modify them directly. The proper thing to do is to<br>
> emit a libcall.<br>
><br>
> This fixes PR17481.<br>
><br>
> Modified:<br>
> llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
> llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp<br>
><br>
> Modified: llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h?rev=192957&r1=192956&r2=192957&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h?rev=192957&r1=192956&r2=192957&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h (original)<br>
> +++ llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h Fri Oct 18 03:03:43 2013<br>
> @@ -325,34 +325,42 @@ namespace RTLIB {<br>
> SYNC_VAL_COMPARE_AND_SWAP_2,<br>
> SYNC_VAL_COMPARE_AND_SWAP_4,<br>
> SYNC_VAL_COMPARE_AND_SWAP_8,<br>
> + SYNC_VAL_COMPARE_AND_SWAP_16,<br>
> SYNC_LOCK_TEST_AND_SET_1,<br>
> SYNC_LOCK_TEST_AND_SET_2,<br>
> SYNC_LOCK_TEST_AND_SET_4,<br>
> SYNC_LOCK_TEST_AND_SET_8,<br>
> + SYNC_LOCK_TEST_AND_SET_16,<br>
> SYNC_FETCH_AND_ADD_1,<br>
> SYNC_FETCH_AND_ADD_2,<br>
> SYNC_FETCH_AND_ADD_4,<br>
> SYNC_FETCH_AND_ADD_8,<br>
> + SYNC_FETCH_AND_ADD_16,<br>
> SYNC_FETCH_AND_SUB_1,<br>
> SYNC_FETCH_AND_SUB_2,<br>
> SYNC_FETCH_AND_SUB_4,<br>
> SYNC_FETCH_AND_SUB_8,<br>
> + SYNC_FETCH_AND_SUB_16,<br>
> SYNC_FETCH_AND_AND_1,<br>
> SYNC_FETCH_AND_AND_2,<br>
> SYNC_FETCH_AND_AND_4,<br>
> SYNC_FETCH_AND_AND_8,<br>
> + SYNC_FETCH_AND_AND_16,<br>
> SYNC_FETCH_AND_OR_1,<br>
> SYNC_FETCH_AND_OR_2,<br>
> SYNC_FETCH_AND_OR_4,<br>
> SYNC_FETCH_AND_OR_8,<br>
> + SYNC_FETCH_AND_OR_16,<br>
> SYNC_FETCH_AND_XOR_1,<br>
> SYNC_FETCH_AND_XOR_2,<br>
> SYNC_FETCH_AND_XOR_4,<br>
> SYNC_FETCH_AND_XOR_8,<br>
> + SYNC_FETCH_AND_XOR_16,<br>
> SYNC_FETCH_AND_NAND_1,<br>
> SYNC_FETCH_AND_NAND_2,<br>
> SYNC_FETCH_AND_NAND_4,<br>
> SYNC_FETCH_AND_NAND_8,<br>
> + SYNC_FETCH_AND_NAND_16,<br>
><br>
> // Stack Protector Fail.<br>
> STACKPROTECTOR_CHECK_FAIL,<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=192957&r1=192956&r2=192957&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=192957&r1=192956&r2=192957&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 18 03:03:43 2013<br>
> @@ -2661,6 +2661,7 @@ std::pair <SDValue, SDValue> SelectionDA<br>
> case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_CMP_SWAP:<br>
> @@ -2670,6 +2671,7 @@ std::pair <SDValue, SDValue> SelectionDA<br>
> case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_ADD:<br>
> @@ -2679,6 +2681,7 @@ std::pair <SDValue, SDValue> SelectionDA<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_SUB:<br>
> @@ -2688,6 +2691,7 @@ std::pair <SDValue, SDValue> SelectionDA<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_AND:<br>
> @@ -2697,6 +2701,7 @@ std::pair <SDValue, SDValue> SelectionDA<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_OR:<br>
> @@ -2706,6 +2711,7 @@ std::pair <SDValue, SDValue> SelectionDA<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_XOR:<br>
> @@ -2715,6 +2721,7 @@ std::pair <SDValue, SDValue> SelectionDA<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_NAND:<br>
> @@ -2724,6 +2731,7 @@ std::pair <SDValue, SDValue> SelectionDA<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;<br>
> }<br>
> break;<br>
> }<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=192957&r1=192956&r2=192957&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=192957&r1=192956&r2=192957&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Fri Oct 18 03:03:43 2013<br>
> @@ -1194,6 +1194,7 @@ std::pair <SDValue, SDValue> DAGTypeLega<br>
> case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_CMP_SWAP:<br>
> @@ -1203,6 +1204,7 @@ std::pair <SDValue, SDValue> DAGTypeLega<br>
> case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_ADD:<br>
> @@ -1212,6 +1214,7 @@ std::pair <SDValue, SDValue> DAGTypeLega<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_SUB:<br>
> @@ -1221,6 +1224,7 @@ std::pair <SDValue, SDValue> DAGTypeLega<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_AND:<br>
> @@ -1230,6 +1234,7 @@ std::pair <SDValue, SDValue> DAGTypeLega<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_OR:<br>
> @@ -1239,6 +1244,7 @@ std::pair <SDValue, SDValue> DAGTypeLega<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_XOR:<br>
> @@ -1248,6 +1254,7 @@ std::pair <SDValue, SDValue> DAGTypeLega<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;<br>
> }<br>
> break;<br>
> case ISD::ATOMIC_LOAD_NAND:<br>
> @@ -1257,6 +1264,7 @@ std::pair <SDValue, SDValue> DAGTypeLega<br>
> case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;<br>
> case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;<br>
> case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;<br>
> + case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;<br>
> }<br>
> break;<br>
> }<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=192957&r1=192956&r2=192957&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=192957&r1=192956&r2=192957&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Fri Oct 18 03:03:43 2013<br>
> @@ -318,34 +318,42 @@ static void InitLibcallNames(const char<br>
> Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";<br>
> Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";<br>
> Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";<br>
> + Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";<br>
> Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";<br>
> Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";<br>
> Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";<br>
> Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";<br>
> + Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";<br>
> Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";<br>
> Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";<br>
> Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";<br>
> Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";<br>
> + Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";<br>
> Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";<br>
> Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";<br>
> Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";<br>
> Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";<br>
> + Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";<br>
> Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";<br>
> Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";<br>
> Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";<br>
> Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";<br>
> + Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";<br>
> Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";<br>
> Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";<br>
> Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";<br>
> Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";<br>
> + Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";<br>
> Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";<br>
> Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";<br>
> Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";<br>
> Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";<br>
> + Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";<br>
> Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";<br>
> Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";<br>
> Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";<br>
> Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";<br>
> + Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";<br>
><br>
> if (Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU) {<br>
> Names[RTLIB::SINCOS_F32] = "sincosf";<br>
><br>
><br>
> _______________________________________________<br>
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> <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
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</div></div></blockquote></div><br></div>