[PATCH] Adding TableGen patterns to auto-select TBM instructions
Kay Tiong Khoo
kkhoo at perfwizard.com
Tue Oct 1 09:51:32 PDT 2013
Yes, the AMD doc (24594_APM_v3, Rev 3.20 May 2013, P. 91) says:
"The BLCI instruction effectively performs a bit-wise logical or of the
source operand and the inverse of the result of incrementing the source
operand by 1, and stores the result to the destination register:
add tmp, src, 1
not tmp, tmp
or dest, tmp, src"
They also specify:
"The value of the carry flag of rFLAGS is generated according to the result
of the add pseudo- instruction and the remaining arithmetic flags are
generated by the or pseudo-instruction."
Does that need to be encoded in the definition somehow?
On Mon, Sep 30, 2013 at 9:19 PM, Craig Topper <craig.topper at gmail.com>wrote:
> While this probably mathematically correct.
> def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
> (BLCI_32rr GR32:$src)>;
> def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
> (BLCI_64rr GR64:$src)>;
> Don't the docs from AMD say something that would be (or GR64:$src, (not
> (add GR64:$src, 1)))?
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> llvm-commits at cs.uiuc.edu
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