[PATCH] [AArch64] Add Register Operand to constrain registers to V0-V15 range
apazos at codeaurora.org
Wed Sep 25 17:08:55 PDT 2013
Hi Tim, Jiangning,
I noted that in Jiangning's latest patch below the constraining of V0-V15 range was done by duplicating the FPR64 and FPR128 register class and truncating them to indexes 0-15.
I also needed such constraint in the implementation of Scalar-by-elem arithmetic instructions.
But I implemented it differently, I used RegisterOperand class instead.
See if you find this solution better and if it satisfies the instructions Jiangning implemented.
From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Jiangning Liu
Sent: Wednesday, September 25, 2013 2:27 AM
To: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
Subject: Re: [PATCH] Implement aarch64 neon instruction class AdvSIMD (by element) - LLVM
Jiangning added you to the CC list for the revision "Implement aarch64 neon instruction class AdvSIMD (by element) - LLVM".
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