[PATCH] Added a new register class for Thumb PC-rel loads

[Daniel Stewart]

Hi Tilmann,

 

I've corrected the stylistic problems in the attached patch.

 

Daniel

 

From: Tilmann Scheller [mailto:tscheller at apple.com] 
Sent: Wednesday, September 04, 2013 2:06 PM
To: Daniel Stewart
Cc: Renato Golin; Commits
Subject: Re: [PATCH] Added a new register class for Thumb PC-rel loads

 

Hi Daniel,

 

minor stylistic nitpicks:

  - Local variables should start with an upper case letter

  - cnstrn: What about a more descriptive variable name here? :)

 

diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp
b/lib/Target/ARM/Thumb2InstrInfo.cpp

index 286eaa0..8861eef 100644

--- a/lib/Target/ARM/Thumb2InstrInfo.cpp

+++ b/lib/Target/ARM/Thumb2InstrInfo.cpp

@@ -152,7 +152,13 @@ storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,

     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp

     // otherwise).

     MachineRegisterInfo *MRI = &MF.getRegInfo();

-    MRI->constrainRegClass(SrcReg,
&ARM::GPRPair_with_gsub_1_in_rGPRRegClass);

+    const TargetRegisterClass* targetClass =
TRI->getMatchingSuperRegClass(RC,

+                                &ARM::rGPRRegClass,

+                                ARM::gsub_1);

+    assert(targetClass && "No Matching GPRPair with gsub_1 in
rGPRRegClass");

+    const TargetRegisterClass* cnstrn =

+                                MRI->constrainRegClass(SrcReg,
targetClass);

+    assert(cnstrn && "Couldn't constrain the register class");

 

     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));

     AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);

@@ -193,7 +199,13 @@ loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,

     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp

     // otherwise).

     MachineRegisterInfo *MRI = &MF.getRegInfo();

-    MRI->constrainRegClass(DestReg,
&ARM::GPRPair_with_gsub_1_in_rGPRRegClass);

+    const TargetRegisterClass* targetClass =
TRI->getMatchingSuperRegClass(RC,

+                                &ARM::rGPRRegClass,

+                                ARM::gsub_1);

+    assert(targetClass && "No Matching GPRPair with gsub_1 in
rGPRRegClass");

+    const TargetRegisterClass* cnstrn =

+                                MRI->constrainRegClass(DestReg,
targetClass);

+    assert(cnstrn && "Couldn't constrain the register class");

 

     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));

     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);

 

Regards,

 

Tilmann

 

On Sep 4, 2013, at 5:50 PM, Daniel Stewart <stewartd at codeaurora.org> wrote:





Attached is the patch with the added test case. My apologies for the delay.

 

Daniel

 

From:  <mailto:llvm-commits-bounces at cs.uiuc.edu>
llvm-commits-bounces at cs.uiuc.edu [ <mailto:llvm-commits-bounces at cs.uiuc.edu>
mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Daniel Stewart
Sent: Friday, August 30, 2013 4:47 PM
To: 'Renato Golin'
Cc: 'Commits'
Subject: RE: [PATCH] Added a new register class for Thumb PC-rel loads

 

Yes, I'll add a test case.

 

Daniel

 

From: Renato Golin [ <mailto:renato.golin at linaro.org>
mailto:renato.golin at linaro.org] 
Sent: Friday, August 30, 2013 4:43 PM
To: Daniel Stewart
Cc: Commits; Jim Grosbach; Evan Cheng
Subject: Re: [PATCH] Added a new register class for Thumb PC-rel loads

 

On 30 August 2013 21:14, Daniel Stewart < <mailto:stewartd at codeaurora.org>
stewartd at codeaurora.org> wrote:

I updated the patch per Jim's suggestions.

 

If this is acceptable, could someone commit it for me, as I do not have
permissions.

 

Hi Daniel,

 

Is it possible to add a test?

 

cheers,

--renato

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