[PATCH] Hexagon Register Cleanup

[Krzysztof Parzyszek]

On 5/13/2013 12:18 PM, Tom Stellard wrote:
>
> We have the exact same problem for the VLIW4/5 subtargets in R600.
> Instructions that write to different sub registers of the same super
> register cannot be scheduled together in the same packet.  Vincent has
> written a patch to fix this in LLVM core. The latest version that was sent
> to the list is here:
> http://permalink.gmane.org/gmane.comp.compilers.llvm.cvs/141708
>
> But Vincent may be able to point you to a more up to date version.

The original intent of this patch was that it will eventually be 
eliminated when the liveness analysis tracks register lanes.  I haven't 
looked at the patch, but is that what it tries to do?

We've had this one running for over 6 months and we would need to make 
sure that we still get the performance with any potential replacement.

-Krzysztof


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