[PATCH] Hexagon Register Cleanup

[Tom Stellard]

On Mon, May 13, 2013 at 12:42:53PM -0500, Krzysztof Parzyszek wrote:
> On 5/13/2013 12:18 PM, Tom Stellard wrote:
> >
> >We have the exact same problem for the VLIW4/5 subtargets in R600.
> >Instructions that write to different sub registers of the same super
> >register cannot be scheduled together in the same packet.  Vincent has
> >written a patch to fix this in LLVM core. The latest version that was sent
> >to the list is here:
> >http://permalink.gmane.org/gmane.comp.compilers.llvm.cvs/141708
> >
> >But Vincent may be able to point you to a more up to date version.
> 
> The original intent of this patch was that it will eventually be
> eliminated when the liveness analysis tracks register lanes.  I
> haven't looked at the patch, but is that what it tries to do?
>

I don't understand very well what the patch is doing, maybe Vincent can
answer this.

> We've had this one running for over 6 months and we would need to
> make sure that we still get the performance with any potential
> replacement.
>

Ok, we should make sure to coordinate testing then, once a final version
of this patch is ready to be committed.

-Tom