Question on direct types in patterns

[Christian König]

I've tried the same for R600/SI and run into exactly the same problems.

The only solution I can see so far is to lose tablegen type constraints in this case.

Cheers,
Christian.

Ulrich Weigand <Ulrich.Weigand at de.ibm.com> schrieb:

>
>Hi Jakob,
>
>we've now managed to remove nearly all instances of register classes in
>patterns in the PowerPC back-end.  However, there is one type of usage
>remaining in PPCInstrAltivec.td:
>
>// Bit conversions.
>def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
>def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
>def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
>
>def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
>def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
>def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
>
>def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
>def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
>def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
>
>def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
>def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
>def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
>
>
>No matter what I tried, I was unable to implement these patterns with
>direct types instead of using the VRRC register class; I'm always getting a
>TableGen error along the lines of:
>Type inference contradiction found, merging 'v8i16' into 'v16i8'
>
>Any suggestion how to handle this case?
>
>Thanks,
>Ulrich
>
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