Question on direct types in patterns

[Jakob Stoklund Olesen]

On Apr 3, 2013, at 10:34 AM, Ulrich Weigand <Ulrich.Weigand at de.ibm.com> wrote:

> we've now managed to remove nearly all instances of register classes in
> patterns in the PowerPC back-end.

Neat!

> However, there is one type of usage remaining in PPCInstrAltivec.td:
> 
> // Bit conversions.
> def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
> def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
> def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
> 
> def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
> def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
> def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
> 
> def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
> def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
> def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
> 
> def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
> def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
> def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
> 
> 
> No matter what I tried, I was unable to implement these patterns with
> direct types instead of using the VRRC register class; I'm always getting a
> TableGen error along the lines of:
> Type inference contradiction found, merging 'v8i16' into 'v16i8'

Yeah, I am afraid TableGen has a giant hack that basically disables type inference for exactly those patterns.

I used this hack for SPARC v9:

  def : Pat<(i64 (anyext i32:$val)), (COPY $val)>;
  def : Pat<(i32 (trunc i64:$val)), (COPY $val)>;

But I am not very happy with it. Emitting extra copy instructions because the instruction selector's idea of a type system doesn't match reality seems like a bad idea.

It's the type checking of output patterns that's causing problems. Suggestions welcome.

/jakob